FastISel.cpp Source File (original) (raw)

104#include

105#include

106#include

107#include

108#include

109

110using namespace llvm;

112

113#define DEBUG_TYPE "isel"

114

115 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "

116 "target-independent selector");

117 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "

118 "target-specific selector");

119 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");

120

121

122

125 "local values should be cleared after finishing a BB");

126

127

128

129

134}

135

137

139 if ( FuncInfo .CanLowerReturn)

140

141

142 return false;

143

145 return false;

146

147

150 I != E; ++I) {

153 FuncInfo.ValueMap[&*I] = VI->second;

154 }

155 return true;

156}

157

158

159

160

164 if (!MO.isReg())

165 continue;

166 if (MO.isDef()) {

167 if (RegDef)

169 RegDef = MO.getReg();

170 } else if (MO.getReg().isVirtual()) {

171

173 }

174 }

175 return RegDef;

176}

177

181 if (P.second == DefReg)

182 return true;

183 return false;

184}

185

186void FastISel::flushLocalValueMap() {

187

188

190

192 ++FirstNonValue;

193

198 for (MachineInstr &LocalMI :

201 if (!DefReg)

202 continue;

203 if (FuncInfo.RegsWithFixups.count(DefReg))

204 continue;

206 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {

209 LLVM_DEBUG(dbgs() << "removing dead local value materialization"

210 << LocalMI);

211 LocalMI.eraseFromParent();

212 }

213 }

214

215 if (FirstNonValue != FuncInfo.MBB->end()) {

216

217

218

219

220

221

222

223

224

228 if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())

229 FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());

230 }

231 }

232

236 SavedInsertPt = FuncInfo.InsertPt;

237}

238

240 EVT RealVT = TLI.getValueType(DL, V->getType(), true);

241

244

245

246

247

249 if ( TLI .isTypeLegal(VT)) {

250

251 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)

252 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();

253 else

255 }

256

257

259 if (Reg)

260 return Reg;

261

262

263

267 return FuncInfo.InitializeRegForValue(V);

268

270

271

272

273 Reg = materializeRegForValue(V, VT);

274

276

277 return Reg;

278}

279

280Register FastISel::materializeConstant(const Value *V, MVT VT) {

283 if (CI->getValue().getActiveBits() <= 64)

288

289

293 if (CF->isNullValue())

295 else

296

298

299 if ( Reg ) {

300

301 const APFloat &Flt = CF->getValueAPF();

304 APSInt SIntVal(IntBitWidth, false);

305 bool isExact;

307 if (isExact) {

309 getRegForValue(ConstantInt::get(V->getContext(), SIntVal));

310 if (IntegerReg)

312 IntegerReg);

313 }

314 }

324 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);

325 }

326 return Reg;

327}

328

329

330

331

332Register FastISel::materializeRegForValue(const Value *V, MVT VT) {

334

337

338

339

340 if ( Reg )

341 Reg = materializeConstant(V, VT);

342

343

344

345 if (Reg) {

348 }

349 return Reg;

350}

351

353

354

355

356

358 if (I != FuncInfo.ValueMap.end())

359 return I->second;

361}

362

366 return;

367 }

368

370 if (!AssignedReg)

371

372 AssignedReg = Reg;

373 else if (Reg != AssignedReg) {

374

375 for (unsigned i = 0; i < NumRegs; i++) {

376 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;

377 FuncInfo.RegsWithFixups.insert(Reg + i);

378 }

379

380 AssignedReg = Reg;

381 }

382}

383

386 if (!IdxN)

387

389

390

392 if (IdxVT.bitsLT(PtrVT)) {

394 } else if (IdxVT.bitsGT(PtrVT)) {

395 IdxN =

397 }

398 return IdxN;

399}

400

409

412 assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&

413 "Invalid iterator!");

414 while (I != E) {

415 if (SavedInsertPt == I)

416 SavedInsertPt = E;

418 EmitStartPt = E.isValid() ? &*E : nullptr;

421

423 ++I;

424 Dead->eraseFromParent();

425 ++NumFastIselDead;

426 }

428}

429

433 return OldInsertPt;

434}

435

439

440

441 FuncInfo.InsertPt = OldInsertPt;

442}

443

445 EVT VT = EVT::getEVT(I->getType(), true);

446 if (VT == MVT::Other || !VT.isSimple())

447

448 return false;

449

450

451

452

453

454 if ( TLI .isTypeLegal(VT)) {

455

456

458 VT = TLI.getTypeToTransformTo(I->getContext(), VT);

459 else

460 return false;

461 }

462

463

464

468 if (!Op1)

469 return false;

470

474 if (!ResultReg)

475 return false;

476

477

479 return true;

480 }

481

483 if (!Op0)

484 return false;

485

486

488 uint64_t Imm = CI->getSExtValue();

489

490

495 }

496

497

500 --Imm;

502 }

503

506 if (!ResultReg)

507 return false;

508

509

511 return true;

512 }

513

515 if (!Op1)

516 return false;

517

518

520 ISDOpcode, Op0, Op1);

521 if (!ResultReg)

522

523

524 return false;

525

526

528 return true;

529}

530

533 if ()

534 return false;

535

536

537

539 return false;

540

541

542

544

546 MVT VT = TLI.getValueType(DL, I->getType()).getSimpleVT();

547

549 GTI != E; ++GTI) {

550 const Value *Idx = GTI.getOperand();

551 if (StructType *StTy = GTI.getStructTypeOrNull()) {

554

555 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);

556 if (TotalOffs >= MaxOffs) {

558 if ()

559 return false;

560 TotalOffs = 0;

561 }

562 }

563 } else {

564

566 if (CI->isZero())

567 continue;

568

569 uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();

570 TotalOffs += GTI.getSequentialElementStride(DL) * IdxN;

571 if (TotalOffs >= MaxOffs) {

573 if ()

574 return false;

575 TotalOffs = 0;

576 }

577 continue;

578 }

579 if (TotalOffs) {

581 if ()

582 return false;

583 TotalOffs = 0;

584 }

585

586

587 uint64_t ElementSize = GTI.getSequentialElementStride(DL);

589 if (!IdxN)

590 return false;

591

592 if (ElementSize != 1) {

594 if (!IdxN)

595 return false;

596 }

598 if ()

599 return false;

600 }

601 }

602 if (TotalOffs) {

604 if ()

605 return false;

606 }

607

608

610 return true;

611}

612

614 const CallInst *CI, unsigned StartIdx) {

615 for (unsigned i = StartIdx, e = CI->arg_size(); i != e; ++i) {

617

625

626

627

628 auto SI = FuncInfo.StaticAllocaMap.find(AI);

629 if (SI != FuncInfo.StaticAllocaMap.end())

631 else

632 return false;

633 } else {

635 if ( Reg )

636 return false;

638 }

639 }

640 return true;

641}

642

644

645

646 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&

647 "Stackmap cannot return a value.");

648

649

650

651

652

653

654

655

656

657

658

660

661

663 "Expected a constant integer.");

666

668 "Expected a constant integer.");

669 const auto *NumBytes =

672

673

674

675 if (!addStackMapLiveVars(Ops, I, 2))

676 return false;

677

678

679

680

681

683 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);

684 for (unsigned i = 0; ScratchRegs[i]; ++i)

686 ScratchRegs[i], true, true, false,

687 false, false, true));

688

689

690 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();

691 auto Builder =

694 for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)

695 Builder.addImm(0);

696

697

699 TII.get(TargetOpcode::STACKMAP));

700 for (auto const &MO : Ops)

701 MIB.add(MO);

702

703

704 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();

708

709

710 FuncInfo.MF->getFrameInfo().setHasStackMap();

711

712 return true;

713}

714

715

716

717

718

719

720bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,

721 unsigned NumArgs, const Value *Callee,

722 bool ForceRetVoidTy, CallLoweringInfo &CLI) {

723 ArgListTy Args;

724 Args.reserve(NumArgs);

725

726

727 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; ArgI != ArgE; ++ArgI) {

729

730 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");

731

733 Entry.setAttributes(CI, ArgI);

734 Args.push_back(Entry);

735 }

736

739 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);

740

742}

743

749 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);

750 return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);

751}

752

754

755

756

757

758

759

762 bool HasDef = ->getType()->isVoidTy();

764

765

767 if (IsAnyRegCC && HasDef) {

768 ValueType = TLI.getSimpleValueType(DL, I->getType(), true);

770 return false;

771 }

772

773

775 "Expected a constant integer.");

776 const auto *NumArgsVal =

778 unsigned NumArgs = NumArgsVal->getZExtValue();

779

780

781

783 assert(I->arg_size() >= NumMetaOpers + NumArgs &&

784 "Not enough arguments provided to the patchpoint intrinsic");

785

786

787 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;

790 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))

791 return false;

792

793 assert(CLI.Call && "No call instruction specified.");

794

796

797

798 if (IsAnyRegCC && HasDef) {

804 }

805

806

808 "Expected a constant integer.");

811

813 "Expected a constant integer.");

814 const auto *NumBytes =

817

818

824 if (C->getOpcode() == Instruction::IntToPtr) {

828 } else

834 else

836

837

838

839 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();

841

842

844

845

846

847 if (IsAnyRegCC) {

848 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {

850 if (!Reg)

851 return false;

853 }

854 }

855

856

857 for (auto Reg : CLI.OutRegs)

859

860

861 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))

862 return false;

863

864

866 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));

867

868

869 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);

870 for (unsigned i = 0; ScratchRegs[i]; ++i)

872 ScratchRegs[i], true, true, false,

873 false, false, true));

874

875

876 for (auto Reg : CLI.InRegs)

878 true));

879

880

882 TII.get(TargetOpcode::PATCHPOINT));

883

884 for (auto &MO : Ops)

885 MIB.add(MO);

886

888

889

891

892

893 FuncInfo.MF->getFrameInfo().setHasPatchPoint();

894

897 return true;

898}

899

901 const auto &Triple = TM.getTargetTriple();

903 return true;

906 false));

908 false));

911 TII.get(TargetOpcode::PATCHABLE_EVENT_CALL));

912 for (auto &MO : Ops)

913 MIB.add(MO);

914

915

916 return true;

917}

918

920 const auto &Triple = TM.getTargetTriple();

922 return true;

925 false));

927 false));

929 false));

932 TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));

933 for (auto &MO : Ops)

934 MIB.add(MO);

935

936

937 return true;

938}

939

940

941

945 Attrs.push_back(Attribute::SExt);

947 Attrs.push_back(Attribute::ZExt);

949 Attrs.push_back(Attribute::InReg);

950

951 return AttributeList::get(CLI.RetTy->getContext(), AttributeList::ReturnIndex,

952 Attrs);

953}

954

956 unsigned NumArgs) {

960 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);

962}

963

965 unsigned NumArgs) {

968

970 Args.reserve(NumArgs);

971

972

973

974 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {

976

977 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");

978

980 Entry.setAttributes(CI, ArgI);

981 Args.push_back(Entry);

982 }

984

986 CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), *CI, NumArgs);

987

989}

990

992

996

999

1000 bool CanLowerReturn = TLI.CanLowerReturn(

1002

1003

1004 if (!CanLowerReturn)

1005 return false;

1006

1007 for (EVT VT : RetTys) {

1009 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);

1010 for (unsigned i = 0; i != NumRegs; ++i) {

1015 Flags.setZExt();

1017 Flags.setInReg();

1020 CLI.Ins.push_back(Ret);

1021 }

1022 }

1023

1024

1026 for (auto &Arg : CLI.getArgs()) {

1027 Type *FinalType = Arg.Ty;

1028 if (Arg.IsByVal)

1029 FinalType = Arg.IndirectType;

1030 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(

1032

1034 if (Arg.IsZExt)

1036 if (Arg.IsSExt)

1037 Flags.setSExt();

1038 if (Arg.IsInReg)

1039 Flags.setInReg();

1040 if (Arg.IsSRet)

1041 Flags.setSRet();

1042 if (Arg.IsSwiftSelf)

1043 Flags.setSwiftSelf();

1044 if (Arg.IsSwiftAsync)

1045 Flags.setSwiftAsync();

1046 if (Arg.IsSwiftError)

1047 Flags.setSwiftError();

1048 if (Arg.IsCFGuardTarget)

1049 Flags.setCFGuardTarget();

1050 if (Arg.IsByVal)

1051 Flags.setByVal();

1052 if (Arg.IsInAlloca) {

1053 Flags.setInAlloca();

1054

1055

1056

1057

1058

1059 Flags.setByVal();

1060 }

1061 if (Arg.IsPreallocated) {

1062 Flags.setPreallocated();

1063

1064

1065

1066

1067

1068 Flags.setByVal();

1069 }

1070 MaybeAlign MemAlign = Arg.Alignment;

1071 if (Arg.IsByVal || Arg.IsInAlloca || Arg.IsPreallocated) {

1072 unsigned FrameSize = DL.getTypeAllocSize(Arg.IndirectType);

1073

1074

1075

1076 if (!MemAlign)

1077 MemAlign = TLI.getByValTypeAlignment(Arg.IndirectType, DL);

1078 Flags.setByValSize(FrameSize);

1079 } else if (!MemAlign) {

1080 MemAlign = DL.getABITypeAlign(Arg.Ty);

1081 }

1082 Flags.setMemAlign(*MemAlign);

1083 if (Arg.IsNest)

1084 Flags.setNest();

1085 if (NeedsRegBlock)

1086 Flags.setInConsecutiveRegs();

1087 Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));

1089 CLI.OutFlags.push_back(Flags);

1090 }

1091

1093 return false;

1094

1095

1096 assert(CLI.Call && "No call instruction specified.");

1098

1101

1102

1103 if (CLI.CB)

1106

1107 return true;

1108}

1109

1113

1115 Args.reserve(CI->arg_size());

1116

1117 for (auto i = CI->arg_begin(), e = CI->arg_end(); i != e; ++i) {

1119

1120

1121 if (V->getType()->isEmptyTy())

1122 continue;

1123

1125

1126 Entry.setAttributes(CI, i - CI->arg_begin());

1127 Args.push_back(Entry);

1128 }

1129

1130

1131

1134 IsTailCall = false;

1136 MF->getFunction().getFnAttribute("disable-tail-calls").getValueAsBool())

1137 IsTailCall = false;

1138

1142

1145 return true;

1146 }

1147

1148 return false;

1149}

1150

1153

1154

1156

1157 if (!IA->getConstraintString().empty())

1158 return false;

1159

1160 unsigned ExtraInfo = 0;

1161 if (IA->hasSideEffects())

1163 if (IA->isAlignStack())

1165 if (Call->isConvergent())

1168

1170 TII.get(TargetOpcode::INLINEASM));

1172 MIB.addImm(ExtraInfo);

1173

1174 const MDNode *SrcLoc = Call->getMetadata("srcloc");

1175 if (SrcLoc)

1177

1178 return true;

1179 }

1180

1181

1184

1186}

1187

1189 if (->hasDbgRecords())

1190 return;

1191

1192

1194

1195

1197 flushLocalValueMap();

1199

1201 assert(DLR->getLabel() && "Missing label");

1203 TII.get(TargetOpcode::DBG_LABEL))

1205 continue;

1206 }

1207

1209

1210 Value *V = nullptr;

1213

1214 bool Res = false;

1219 } else {

1221 if (FuncInfo.PreprocessedDVRDeclares.contains(&DVR))

1222 continue;

1225 }

1226

1227 if (!Res)

1228 LLVM_DEBUG(dbgs() << "Dropping debug-info for " << DVR << "\n");

1229 }

1230}

1231

1234

1237

1238

1240 return true;

1241 }

1243

1244 if (Expr)

1245 std::tie(Expr, CI) = Expr->constantFold(CI);

1246 if (CI->getBitWidth() > 64)

1252 else

1254 .addImm(CI->getZExtValue())

1258 return true;

1259 }

1266 return true;

1267 }

1270

1271 assert(Arg->hasAttribute(Attribute::AttrKind::SwiftAsync));

1272

1274 for (auto [PhysReg, VirtReg] : FuncInfo.RegInfo->liveins())

1275 if (Reg == VirtReg || Reg == PhysReg) {

1277 PhysReg, Var, Expr);

1278 return true;

1279 }

1280

1281 LLVM_DEBUG(dbgs() << "Dropping dbg.value: expression is entry_value but "

1282 "couldn't find a physical register\n");

1283 return false;

1284 }

1286 SI != FuncInfo.StaticAllocaMap.end()) {

1288 bool IsIndirect = false;

1290 Var, Expr);

1291 return true;

1292 }

1294

1295 if ( FuncInfo .MF->useDebugInstrRef()) {

1296 bool IsIndirect = false;

1298 Expr);

1299 return true;

1300 }

1301

1302

1304 Reg, false, false,

1305 false, false,

1306 false, false,

1307 0, true)});

1311 TII.get(TargetOpcode::DBG_INSTR_REF), false, MOs,

1313 return true;

1314 }

1315 return false;

1316}

1317

1321 LLVM_DEBUG(dbgs() << "Dropping debug info (bad/undef address)\n");

1322 return false;

1323 }

1324

1325 std::optional Op;

1328

1329

1330

1331

1332

1333

1334

1335

1336

1337

1338

1339

1344 false);

1345

1346 if (Op) {

1348 "Expected inlined-at fields to agree");

1349 if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) {

1350

1351

1352

1357 TII.get(TargetOpcode::DBG_INSTR_REF), false, *Op,

1359 return true;

1360 }

1361

1362

1363

1365 TII.get(TargetOpcode::DBG_VALUE), true, *Op, Var,

1366 Expr);

1367 return true;

1368 }

1369

1370

1371

1373 dbgs() << "Dropping debug info (no materialized reg for address)\n");

1374 return false;

1375}

1376

1378 switch (II->getIntrinsicID()) {

1379 default:

1380 break;

1381

1382 case Intrinsic::lifetime_start:

1383 case Intrinsic::lifetime_end:

1384

1385 case Intrinsic::donothing:

1386

1387 case Intrinsic::sideeffect:

1388

1389 case Intrinsic::assume:

1390

1391 case Intrinsic::experimental_noalias_scope_decl:

1392 return true;

1393 case Intrinsic::objectsize:

1394 llvm_unreachable("llvm.objectsize.* should have been lowered already");

1395

1396 case Intrinsic::is_constant:

1397 llvm_unreachable("llvm.is.constant.* should have been lowered already");

1398

1399 case Intrinsic::allow_runtime_check:

1400 case Intrinsic::allow_ubsan_check: {

1402 if (!ResultReg)

1403 return false;

1405 return true;

1406 }

1407

1408 case Intrinsic::launder_invariant_group:

1409 case Intrinsic::strip_invariant_group:

1410 case Intrinsic::expect:

1411 case Intrinsic::expect_with_probability: {

1413 if (!ResultReg)

1414 return false;

1416 return true;

1417 }

1418 case Intrinsic::fake_use:

1419

1420 return true;

1421 case Intrinsic::experimental_stackmap:

1423 case Intrinsic::experimental_patchpoint_void:

1424 case Intrinsic::experimental_patchpoint:

1426

1427 case Intrinsic::xray_customevent:

1429 case Intrinsic::xray_typedevent:

1431 }

1432

1434}

1435

1437 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());

1438 EVT DstVT = TLI.getValueType(DL, I->getType());

1439

1440 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||

1442

1443 return false;

1444

1445

1446 if ( TLI .isTypeLegal(DstVT))

1447 return false;

1448

1449

1450 if ( TLI .isTypeLegal(SrcVT))

1451 return false;

1452

1454 if (!InputReg)

1455

1456 return false;

1457

1459 Opcode, InputReg);

1460 if (!ResultReg)

1461 return false;

1462

1464 return true;

1465}

1466

1468 EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());

1469 EVT DstEVT = TLI.getValueType(DL, I->getType());

1470 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||

1471 TLI .isTypeLegal(SrcEVT) || TLI .isTypeLegal(DstEVT))

1472

1473 return false;

1474

1478 if (!Op0)

1479 return false;

1480

1481

1482 if (SrcVT == DstVT) {

1484 return true;

1485 }

1486

1487

1489 if (!ResultReg)

1490 return false;

1491

1493 return true;

1494}

1495

1498 if (!Reg)

1499

1500 return false;

1501

1502 EVT ETy = TLI.getValueType(DL, I->getOperand(0)->getType());

1503 if (ETy == MVT::Other || TLI .isTypeLegal(ETy))

1504

1505 return false;

1506

1511 TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);

1512

1514 return true;

1515}

1516

1517

1518

1519void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)

1520{

1522 if (CurLastLocalValue != SavedLastLocalValue) {

1523

1524

1525

1527 if (SavedLastLocalValue)

1528 ++FirstDeadInst;

1529 else

1533 }

1534}

1535

1537

1538

1539

1540 flushLocalValueMap();

1541

1543

1544

1545 if (I->isTerminator()) {

1546 if (!handlePHINodesInSuccessorBlocks(I->getParent())) {

1547

1548

1549

1550

1551 removeDeadLocalValueCode(SavedLastLocalValue);

1552 return false;

1553 }

1554 }

1555

1556

1558 for (unsigned i = 0, e = Call->getNumOperandBundles(); i != e; ++i)

1560 return false;

1561

1563

1564 SavedInsertPt = FuncInfo.InsertPt;

1565

1568

1569

1570 if (F && F->getIntrinsicID() == Intrinsic::trap &&

1571 Call->hasFnAttr("trap-func-name"))

1572 return false;

1573 }

1574

1575

1578 ++NumFastIselSuccessIndependent;

1580 return true;

1581 }

1582

1584 if (SavedInsertPt != FuncInfo.InsertPt)

1586 SavedInsertPt = FuncInfo.InsertPt;

1587 }

1588

1590 ++NumFastIselSuccessTarget;

1592 return true;

1593 }

1594

1596 if (SavedInsertPt != FuncInfo.InsertPt)

1598

1600

1601 if (I->isTerminator()) {

1602

1603

1604 removeDeadLocalValueCode(SavedLastLocalValue);

1605 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);

1606 }

1607 return false;

1608}

1609

1610

1611

1615 bool BlockHasMultipleInstrs = &BB->front() != &BB->back();

1616 if (BlockHasMultipleInstrs && FuncInfo.MBB->isLayoutSuccessor(MSucc)) {

1617

1618

1619

1620 } else {

1621

1622 TII.insertBranch(*FuncInfo.MBB, MSucc, nullptr,

1624 }

1629 } else

1630 FuncInfo.MBB->addSuccessorWithoutProb(MSucc);

1631}

1632

1636

1637

1638

1639 if (TrueMBB != FalseMBB) {

1644 } else

1645 FuncInfo.MBB->addSuccessorWithoutProb(TrueMBB);

1646 }

1647

1649}

1650

1651

1654 if (!OpReg)

1655 return false;

1656

1657

1658 EVT VT = TLI.getValueType(DL, I->getType());

1660 OpReg);

1661 if (ResultReg) {

1663 return true;

1664 }

1665

1666

1667

1669 return false;

1671 if ( TLI .isTypeLegal(IntVT))

1672 return false;

1673

1675 ISD::BITCAST, OpReg);

1676 if (!IntReg)

1677 return false;

1678

1682 if (!IntResultReg)

1683 return false;

1684

1686 IntResultReg);

1687 if (!ResultReg)

1688 return false;

1689

1691 return true;

1692}

1693

1696 if (!EVI)

1697 return false;

1698

1699

1700

1701 EVT RealVT = TLI.getValueType(DL, EVI->getType(), true);

1703 return false;

1705 if ( TLI .isTypeLegal(VT) && VT != MVT::i1)

1706 return false;

1707

1710

1711

1714 if (I != FuncInfo.ValueMap.end())

1715 ResultReg = I->second;

1717 ResultReg = FuncInfo.InitializeRegForValue(Op0);

1718 else

1719 return false;

1720

1721

1723

1726

1727 for (unsigned i = 0; i < VTIndex; i++)

1728 ResultReg = ResultReg.id() +

1729 TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);

1730

1732 return true;

1733}

1734

1736 switch (Opcode) {

1737 case Instruction::Add:

1739 case Instruction::FAdd:

1741 case Instruction::Sub:

1743 case Instruction::FSub:

1745 case Instruction::Mul:

1747 case Instruction::FMul:

1749 case Instruction::SDiv:

1751 case Instruction::UDiv:

1753 case Instruction::FDiv:

1755 case Instruction::SRem:

1757 case Instruction::URem:

1759 case Instruction::FRem:

1761 case Instruction::Shl:

1763 case Instruction::LShr:

1765 case Instruction::AShr:

1767 case Instruction::And:

1769 case Instruction::Or:

1771 case Instruction::Xor:

1773

1774 case Instruction::FNeg:

1776

1777 case Instruction::GetElementPtr:

1779

1780 case Instruction::Br: {

1782

1787 return true;

1788 }

1789

1790

1791

1792 return false;

1793 }

1794

1795 case Instruction::Unreachable: {

1797 if (!UI->shouldLowerToTrap(TM.Options.TrapUnreachable,

1798 TM.Options.NoTrapAfterNoreturn))

1799 return true;

1800

1801 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;

1802 }

1803

1804 case Instruction::Alloca:

1805

1807 return true;

1808

1809

1810 return false;

1811

1812 case Instruction::Call:

1813

1814

1815

1816

1817

1818

1820 return false;

1822

1823 case Instruction::BitCast:

1825

1826 case Instruction::FPToSI:

1828 case Instruction::ZExt:

1830 case Instruction::SExt:

1832 case Instruction::Trunc:

1834 case Instruction::SIToFP:

1836

1837 case Instruction::IntToPtr:

1838 case Instruction::PtrToInt:

1839 case Instruction::PtrToAddr: {

1840 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());

1841 EVT DstVT = TLI.getValueType(DL, I->getType());

1842 if (DstVT.bitsGT(SrcVT))

1844 if (DstVT.bitsLT(SrcVT))

1847 if (!Reg)

1848 return false;

1850 return true;

1851 }

1852

1853 case Instruction::ExtractValue:

1855

1856 case Instruction::Freeze:

1858

1859 case Instruction::PHI:

1861

1862 default:

1863

1864 return false;

1865 }

1866}

1867

1874 TII(*MF->getSubtarget().getInstrInfo()),

1875 TLI(*MF->getSubtarget().getTargetLowering()),

1878

1880

1882

1884

1888

1890

1894

1899

1903

1908

1913

1914

1915

1916

1917

1920

1925

1928 }

1929

1930

1931

1935

1936

1938 if (ResultReg)

1939 return ResultReg;

1941 if (!MaterialReg) {

1942

1943

1946 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));

1947 if (!MaterialReg)

1949 }

1950 return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);

1951}

1952

1954 return MRI.createVirtualRegister(RC);

1955}

1956

1958 unsigned OpNum) {

1959 if (Op.isVirtual()) {

1961 if ( MRI .constrainRegClass(Op, RegClass)) {

1962

1963

1966 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);

1967 return NewOp;

1968 }

1969 }

1970 return Op;

1971}

1972

1977

1979 return ResultReg;

1980}

1981

1985

1988

1989 if (II.getNumDefs() >= 1)

1992 else {

1996 ResultReg)

1997 .addReg(II.implicit_defs()[0]);

1998 }

1999

2000 return ResultReg;

2001}

2002

2007

2011

2012 if (II.getNumDefs() >= 1)

2016 else {

2021 ResultReg)

2022 .addReg(II.implicit_defs()[0]);

2023 }

2024 return ResultReg;

2025}

2026

2031

2036

2037 if (II.getNumDefs() >= 1)

2042 else {

2048 ResultReg)

2049 .addReg(II.implicit_defs()[0]);

2050 }

2051 return ResultReg;

2052}

2053

2058

2061

2062 if (II.getNumDefs() >= 1)

2066 else {

2071 ResultReg)

2072 .addReg(II.implicit_defs()[0]);

2073 }

2074 return ResultReg;

2075}

2076

2081

2084

2085 if (II.getNumDefs() >= 1)

2090 else {

2096 ResultReg)

2097 .addReg(II.implicit_defs()[0]);

2098 }

2099 return ResultReg;

2100}

2101

2106

2108

2109 if (II.getNumDefs() >= 1)

2112 else {

2116 ResultReg)

2117 .addReg(II.implicit_defs()[0]);

2118 }

2119 return ResultReg;

2120}

2121

2126

2130

2131 if (II.getNumDefs() >= 1)

2136 else {

2142 ResultReg)

2143 .addReg(II.implicit_defs()[0]);

2144 }

2145 return ResultReg;

2146}

2147

2152

2153 if (II.getNumDefs() >= 1)

2156 else {

2159 ResultReg)

2160 .addReg(II.implicit_defs()[0]);

2161 }

2162 return ResultReg;

2163}

2164

2168 assert(Op0.isVirtual() && "Cannot yet extract from physregs");

2170 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));

2172 ResultReg).addReg(Op0, 0, Idx);

2173 return ResultReg;

2174}

2175

2176

2177

2181

2182

2183

2184

2185

2186

2187

2188bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {

2191

2192

2193

2196 continue;

2198

2199

2200

2201 if (!SuccsHandled.insert(SuccMBB).second)

2202 continue;

2203

2205

2206

2207

2208

2209 for (const PHINode &PN : SuccBB->phis()) {

2210

2211 if (PN.use_empty())

2212 continue;

2213

2214

2215

2216

2217

2218

2219

2222

2223 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {

2225 return false;

2226 }

2227 }

2228

2229 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);

2230

2231

2232

2235 MIMD = MIMetadata(*Inst);

2236

2238 if ( Reg ) {

2239 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);

2240 return false;

2241 }

2244 }

2245 }

2246

2247 return true;

2248}

2249

2252 "tryToFoldLoad expected a LoadInst with a single use");

2253

2254

2255

2256 unsigned MaxUsers = 6;

2257

2259 while (TheUser != FoldInst &&

2260

2262 --MaxUsers) {

2263

2265 return false;

2266

2268 }

2269

2270

2271

2272 if (TheUser != FoldInst)

2273 return false;

2274

2275

2276

2278 return false;

2279

2280

2281

2282

2284 if (!LoadReg)

2285 return false;

2286

2287

2288

2289

2290 if ( MRI .hasOneUse(LoadReg))

2291 return false;

2292

2293

2294

2295 if (FuncInfo.RegsWithFixups.contains(LoadReg))

2296 return false;

2297

2300

2301

2302

2303

2306

2307

2309}

2310

2312

2314 return false;

2315

2316 if (DL.getTypeSizeInBits(GEP->getType()) !=

2317 DL.getTypeSizeInBits(Add->getType()))

2318 return false;

2319

2322 return false;

2323

2325}

2326

2329 const Value *Ptr;

2330 Type *ValTy;

2333 bool IsVolatile;

2334

2336 Alignment = LI->getAlign();

2337 IsVolatile = LI->isVolatile();

2339 Ptr = LI->getPointerOperand();

2342 Alignment = SI->getAlign();

2343 IsVolatile = SI->isVolatile();

2345 Ptr = SI->getPointerOperand();

2346 ValTy = SI->getValueOperand()->getType();

2347 } else

2348 return nullptr;

2349

2350 bool IsNonTemporal = I->hasMetadata(LLVMContext::MD_nontemporal);

2351 bool IsInvariant = I->hasMetadata(LLVMContext::MD_invariant_load);

2352 bool IsDereferenceable = I->hasMetadata(LLVMContext::MD_dereferenceable);

2353 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);

2354

2355 AAMDNodes AAInfo = I->getAAMetadata();

2356

2357 if (!Alignment)

2358 Alignment = DL.getABITypeAlign(ValTy);

2359

2360 unsigned Size = DL.getTypeStoreSize(ValTy);

2361

2362 if (IsVolatile)

2364 if (IsNonTemporal)

2366 if (IsDereferenceable)

2368 if (IsInvariant)

2370

2372 *Alignment, AAInfo, Ranges);

2373}

2374

2376

2379 return Predicate;

2380

2381 switch (Predicate) {

2399

2410 }

2411

2412 return Predicate;

2413}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file declares a class to represent arbitrary precision floating point values and provide a varie...

This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

This file contains the simple types necessary to represent the attributes associated with functions a...

This file contains the declarations for the subclasses of Constant, which represent the different fla...

This file defines the DenseMap class.

static Register findLocalRegDef(MachineInstr &MI)

Return the defined register if this instruction defines exactly one virtual register and uses no othe...

Definition FastISel.cpp:161

static bool isRegUsedByPhiNodes(Register DefReg, FunctionLoweringInfo &FuncInfo)

Definition FastISel.cpp:178

static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)

Returns an AttributeList representing the attributes applied to the return value of the given call.

Definition FastISel.cpp:942

This file defines the FastISel class.

Module.h This file contains the declarations for the Module class.

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Promote Memory to Register

uint64_t IntrinsicInst * II

OptimizedStructLayoutField Field

static bool isCommutative(Instruction *I, Value *ValWithUses, bool IsCopyable=false)

This file defines the SmallPtrSet class.

This file defines the SmallString class.

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

static SymbolRef::Type getType(const Symbol *Sym)

This file describes how to lower LLVM code to machine code.

static constexpr roundingMode rmTowardZero

opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const

An arbitrary precision integer that knows its signedness.

LLVM Basic Block Representation.

const Instruction & back() const

const Instruction & front() const

Conditional or Unconditional Branch instruction.

BasicBlock * getSuccessor(unsigned i) const

bool isUnconditional() const

CallingConv::ID getCallingConv() const

User::op_iterator arg_begin()

Return the iterator pointing to the beginning of the argument list.

Value * getCalledOperand() const

Value * getArgOperand(unsigned i) const

User::op_iterator arg_end()

Return the iterator pointing to the end of the argument list.

FunctionType * getFunctionType() const

unsigned arg_size() const

This class represents a function call, abstracting a target machine's calling convention.

bool isMustTailCall() const

This class is the base class for the comparison instructions.

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

@ FCMP_OEQ

0 0 0 1 True if ordered and equal

@ FCMP_TRUE

1 1 1 1 Always true (always folded)

@ ICMP_SLT

signed less than

@ ICMP_SLE

signed less or equal

@ FCMP_OLT

0 1 0 0 True if ordered and less than

@ FCMP_ULE

1 1 0 1 True if unordered, less than, or equal

@ FCMP_OGT

0 0 1 0 True if ordered and greater than

@ FCMP_OGE

0 0 1 1 True if ordered and greater than or equal

@ ICMP_UGE

unsigned greater or equal

@ ICMP_UGT

unsigned greater than

@ ICMP_SGT

signed greater than

@ FCMP_ULT

1 1 0 0 True if unordered or less than

@ FCMP_ONE

0 1 1 0 True if ordered and operands are unequal

@ FCMP_UEQ

1 0 0 1 True if unordered or equal

@ ICMP_ULT

unsigned less than

@ FCMP_UGT

1 0 1 0 True if unordered or greater than

@ FCMP_OLE

0 1 0 1 True if ordered and less than or equal

@ FCMP_ORD

0 1 1 1 True if ordered (no nans)

@ ICMP_SGE

signed greater or equal

@ FCMP_UNE

1 1 1 0 True if unordered or not equal

@ ICMP_ULE

unsigned less or equal

@ FCMP_UGE

1 0 1 1 True if unordered, greater than, or equal

@ FCMP_FALSE

0 0 0 0 Always false (always folded)

@ FCMP_UNO

1 0 0 0 True if unordered: isnan(X) | isnan(Y)

Predicate getPredicate() const

Return the predicate for this instruction.

ConstantFP - Floating Point Values [float, double].

static LLVM_ABI ConstantInt * getTrue(LLVMContext &Context)

static LLVM_ABI Constant * getNullValue(Type *Ty)

Constructor to create a '0' constant of arbitrary type.

LLVM_ABI bool isEntryValue() const

Check if the expression consists of exactly one entry value operand.

LLVM_ABI std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)

Try to shorten an expression with an initial constant operand.

static LLVM_ABI DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)

Prepend DIExpr with the given opcodes and optionally turn it into a stack value.

bool isValidLocationForIntrinsic(const DILocation *DL) const

Check that a location is valid for this variable.

A parsed version of the target data layout string in and methods for querying it.

Records a position in IR for a source label (DILabel).

Base class for non-instruction debug metadata records that have positions within IR.

DebugLoc getDebugLoc() const

Record of a variable value-assignment, aka a non instruction representation of the dbg....

LocationType getType() const

LLVM_ABI Value * getVariableLocationOp(unsigned OpIdx) const

DIExpression * getExpression() const

DILocalVariable * getVariable() const

DenseMapIterator< KeyT, ValueT, KeyInfoT, BucketT > iterator

MachineRegisterInfo & MRI

const TargetLibraryInfo * LibInfo

bool selectGetElementPtr(const User *I)

Definition FastISel.cpp:531

void setLastLocalValue(MachineInstr *I)

Update the position of the last instruction emitted for materializing constants for use in the curren...

bool selectStackmap(const CallInst *I)

Definition FastISel.cpp:643

Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...

Definition FastISel.cpp:2054

bool selectExtractValue(const User *U)

Definition FastISel.cpp:1694

DenseMap< const Value *, Register > LocalValueMap

void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc)

Emit an unconditional branch to the given block, unless it is the immediate (fall-through) successor,...

Definition FastISel.cpp:1612

MachineInstr * EmitStartPt

The top most instruction in the current block that is allowed for emitting local variables.

bool selectXRayCustomEvent(const CallInst *II)

Definition FastISel.cpp:900

virtual Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0)

This method is called by target-independent code to request that an instruction with the given type,...

Definition FastISel.cpp:1891

Emit a MachineInstr with no operands and a result register in the given register class.

Definition FastISel.cpp:1973

Emit a MachineInstr with two register operands and a result register in the given register class.

Definition FastISel.cpp:2003

virtual Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1)

This method is called by target-independent code to request that an instruction with the given type,...

Definition FastISel.cpp:1895

virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II)

This method is called by target-independent code to do target- specific intrinsic lowering.

Definition FastISel.cpp:1885

virtual bool lowerDbgDeclare(const Value *V, DIExpression *Expr, DILocalVariable *Var, const DebugLoc &DL)

Target-independent lowering of debug information.

Definition FastISel.cpp:1318

MachineInstr * getLastLocalValue()

Return the position of the last instruction emitted for materializing constants for use in the curren...

bool lowerCall(const CallInst *I)

Definition FastISel.cpp:1110

void leaveLocalValueArea(SavePoint Old)

Reset InsertPt to the given old insert position.

Definition FastISel.cpp:436

virtual Register fastMaterializeConstant(const Constant *C)

Emit a constant in a register using target-specific logic, such as constant pool loads.

Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, Register Op0, Register Op1, Register Op2)

Emit a MachineInstr with three register operands and a result register in the given register class.

Definition FastISel.cpp:2027

bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs)

Definition FastISel.cpp:964

virtual Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)

This method is called by target-independent code to request that an instruction with the given type,...

Definition FastISel.cpp:1900

virtual Register fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm)

This method is called by target-independent code to request that an instruction with the given type,...

Definition FastISel.cpp:1904

void handleDbgInfo(const Instruction *II)

Target-independent lowering of non-instruction debug info associated with this instruction.

Definition FastISel.cpp:1188

bool selectFreeze(const User *I)

Definition FastISel.cpp:1496

bool selectIntrinsicCall(const IntrinsicInst *II)

Definition FastISel.cpp:1377

This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the give...

Definition FastISel.cpp:384

bool selectCast(const User *I, unsigned Opcode)

Definition FastISel.cpp:1436

bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)

We're checking to see if we can fold LI into FoldInst.

Definition FastISel.cpp:2250

Create a virtual register and arrange for it to be assigned the value for the given LLVM value.

Definition FastISel.cpp:239

void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)

Remove all dead instructions between the I and E.

Definition FastISel.cpp:410

virtual Register fastMaterializeFloatZero(const ConstantFP *CF)

Emit the floating-point constant +0.0 in a register using target- specific logic.

void startNewBlock()

Set the current block to which generated machine instructions will be appended.

Definition FastISel.cpp:123

MachineMemOperand * createMachineMemOperandFor(const Instruction *I) const

Create a machine mem operand from the given instruction.

Definition FastISel.cpp:2328

virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)

The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...

Emit a MachineInstr with a single immediate operand, and a result register in the given register clas...

Definition FastISel.cpp:2148

Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, Register Op0, uint64_t Imm1, uint64_t Imm2)

Emit a MachineInstr with one register operand and two immediate operands.

Definition FastISel.cpp:2077

bool canFoldAddIntoGEP(const User *GEP, const Value *Add)

Check if Add is an add that can be safely folded into GEP.

Definition FastISel.cpp:2311

virtual bool lowerDbgValue(const Value *V, DIExpression *Expr, DILocalVariable *Var, const DebugLoc &DL)

Target-independent lowering of debug information.

Definition FastISel.cpp:1232

TargetLoweringBase::ArgListTy ArgListTy

bool selectInstruction(const Instruction *I)

Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...

Definition FastISel.cpp:1536

virtual bool fastLowerCall(CallLoweringInfo &CLI)

This method is called by target-independent code to do target- specific call lowering.

Definition FastISel.cpp:1883

bool selectXRayTypedEvent(const CallInst *II)

Definition FastISel.cpp:919

virtual Register fastMaterializeAlloca(const AllocaInst *C)

Emit an alloca address in a register using target-specific logic.

Emit MachineInstrs to compute the value of Op with all but the least significant bit set to zero.

Definition FastISel.cpp:2178

Definition FastISel.cpp:1953

virtual bool fastLowerArguments()

This method is called by target-independent code to do target- specific argument lowering.

Definition FastISel.cpp:1881

bool selectFNeg(const User *I, const Value *In)

Emit an FNeg operation.

Definition FastISel.cpp:1652

const TargetInstrInfo & TII

bool selectCall(const User *I)

Definition FastISel.cpp:1151

Look up the value to see if its value is already cached in a register.

Definition FastISel.cpp:352

CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const

Definition FastISel.cpp:2375

virtual Register fastEmit_(MVT VT, MVT RetVT, unsigned Opcode)

This method is called by target-independent code to request that an instruction with the given type a...

Definition FastISel.cpp:1889

void finishBasicBlock()

Flush the local value map.

Definition FastISel.cpp:136

Emit a MachineInstr with one register operand and a result register in the given register class.

Definition FastISel.cpp:1982

Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, Register Op0, Register Op1, uint64_t Imm)

Emit a MachineInstr with two register operands, an immediate, and a result register in the given regi...

Definition FastISel.cpp:2122

FunctionLoweringInfo & FuncInfo

MachineConstantPool & MCP

bool selectOperator(const User *I, unsigned Opcode)

Do "fast" instruction selection for the given LLVM IR operator (Instruction or ConstantExpr),...

Definition FastISel.cpp:1735

bool SkipTargetIndependentISel

Emit a MachineInstr with a floating point immediate, and a result register in the given register clas...

Definition FastISel.cpp:2102

Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc.

Definition FastISel.cpp:1957

MachineBasicBlock::iterator SavePoint

Emit a MachineInstr for an extract_subreg from a specified index of a superregister to a specified ty...

Definition FastISel.cpp:2165

void updateValueMap(const Value *I, Register Reg, unsigned NumRegs=1)

Update the value map to include the new mapping for this instruction, or insert an extra copy to get ...

Definition FastISel.cpp:363

bool selectBinaryOp(const User *I, unsigned ISDOpcode)

Select and emit code for a binary operator instruction, which has an opcode which directly correspond...

Definition FastISel.cpp:444

FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, bool SkipTargetIndependentISel=false)

Definition FastISel.cpp:1868

bool selectPatchpoint(const CallInst *I)

Definition FastISel.cpp:753

void recomputeInsertPt()

Reset InsertPt to prepare for inserting instructions into the current block.

Definition FastISel.cpp:401

virtual bool fastSelectInstruction(const Instruction *I)=0

This method is called by target-independent code when the normal FastISel process fails to select an ...

const TargetLowering & TLI

virtual Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t Imm)

This method is called by target-independent code to request that an instruction with the given type,...

Definition FastISel.cpp:1909

MachineInstr * LastLocalValue

The position of the last instruction for materializing constants for use in the current block.

bool lowerArguments()

Do "fast" instruction selection for function arguments and append the machine instructions to the cur...

Definition FastISel.cpp:138

SavePoint enterLocalValueArea()

Prepare InsertPt to begin inserting instructions into the local value area and return the old insert ...

Definition FastISel.cpp:430

void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB)

Emit an unconditional branch to FalseMBB, obtains the branch weight and adds TrueMBB and FalseMBB to ...

Definition FastISel.cpp:1633

bool selectBitCast(const User *I)

Definition FastISel.cpp:1467

This method is a wrapper of fastEmit_ri.

Definition FastISel.cpp:1918

const TargetRegisterInfo & TRI

TargetLoweringBase::ArgListEntry ArgListEntry

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

MachineBasicBlock * getMBB(const BasicBlock *BB) const

unsigned OrigNumPHINodesToUpdate

MachineBasicBlock::iterator InsertPt

MBB - The current insert position inside the current block.

MachineBasicBlock * MBB

MBB - The current block.

std::vector< std::pair< MachineInstr *, Register > > PHINodesToUpdate

PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...

Class to represent function types.

const Argument * const_arg_iterator

const DebugLoc & getDebugLoc() const

Return the debug location for this node as a DebugLoc.

Instruction * user_back()

Specialize the methods defined in Value, as we know that an instruction can only be used by other ins...

MDNode * getMetadata(unsigned KindID) const

Get the metadata of given kind attached to this Instruction.

Class to represent integer types.

static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)

This static method is the primary way of constructing an IntegerType.

A wrapper class for inspecting calls to intrinsic functions.

An instruction for reading from memory.

bool isVolatile() const

Return true if this is a load from a volatile memory location.

Context object for machine code objects.

Describe properties that are true of each instruction in the target description file.

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

LLVM_ABI iterator getFirstNonPHI()

Returns a pointer to the first instruction in this block that is not a PHINode instruction.

MachineInstrBundleIterator< MachineInstr, true > reverse_iterator

MachineInstrBundleIterator< MachineInstr > iterator

const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const

const MachineInstrBuilder & addCImm(const ConstantInt *Val) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addMetadata(const MDNode *MD) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const

Representation of each machine instruction.

LLVM_ABI void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)

Set a marker on instructions that denotes where we should create and emit heap alloc site labels.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

LLVM_ABI void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

A description of a memory reference used in the backend.

Flags

Flags values. These may be or'd together.

@ MOVolatile

The memory access is volatile.

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

@ MOLoad

The memory access reads data.

@ MONonTemporal

The memory access is non-temporal.

@ MOInvariant

The memory access always returns the same value (or traps).

@ MOStore

The memory access writes data.

MachineOperand class - Representation of each machine instruction operand.

static MachineOperand CreateRegMask(const uint32_t *Mask)

CreateRegMask - Creates a register mask operand referencing Mask.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

static MachineOperand CreateImm(int64_t Val)

static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

static MachineOperand CreateFI(int Idx)

unsigned getOperandNo() const

getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.

defusechain_iterator< true, true, false, true, false > reg_iterator

reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.

LLVM_ABI void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const

Print the appropriate prefix and the specified global variable's name.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr unsigned id() const

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

Class to represent struct types.

Provides information about what library functions are available for the current target.

EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

Return the EVT corresponding to this LLVM type.

bool isTypeLegal(EVT VT) const

Return true if the target has native support for the specified value type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

ArchType getArch() const

Get the parsed architecture type of this triple.

bool isAArch64() const

Tests whether the target is AArch64 (little and big endian).

The instances of the Type class are immutable: once they are created, they are never changed.

static LLVM_ABI Type * getVoidTy(LLVMContext &C)

LLVMContext & getContext() const

Return the LLVMContext in which this type was uniqued.

Value * getOperand(unsigned i) const

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

bool hasOneUse() const

Return true if there is exactly one use of this value.

const ParentTy * getParent() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ AnyReg

OBSOLETED - Used for stack based JavaScript calls.

@ C

The default llvm calling convention, compatible with C.

@ ADD

Simple integer binary arithmetic operators.

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ FADD

Simple binary floating point operators.

@ SIGN_EXTEND

Conversion operators.

@ SHL

Shift and rotation operations.

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

bool isBitwiseLogicOp(unsigned Opcode)

Whether this is bitwise logic opcode.

@ DW_OP_LLVM_arg

Only used in LLVM metadata.

std::reverse_iterator< iterator > rend() const

LLVM_ABI iterator begin() const

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

LLVM_ABI void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)

Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs=nullptr, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())

ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI void diagnoseDontCall(const CallInst &CI)

auto successors(const MachineBasicBlock *BB)

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

constexpr bool isPowerOf2_64(uint64_t Value)

Return true if the argument is a power of two > 0 (64 bit edition.)

gep_type_iterator gep_type_end(const User *GEP)

unsigned Log2_64(uint64_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.

auto reverse(ContainerTy &&C)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

generic_gep_type_iterator<> gep_type_iterator

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM, bool ReturnsFirstArg=false)

Test if the given instruction is in a position to be optimized with a tail-call.

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

gep_type_iterator gep_type_begin(const User *GEP)

PointerUnion< const Value *, const PseudoSourceValue * > ValueType

unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)

Compute the linearized index of a member in a nested aggregate/struct/array.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

bool bitsGT(EVT VT) const

Return true if this has more bits than VT.

bool bitsLT(EVT VT) const

Return true if this has less bits than VT.

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

static LLVM_ABI EVT getEVT(Type *Ty, bool HandleUnknown=false)

Return the value type corresponding to the specified type.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)

Returns the EVT that represents an integer with the given number of bits.

SmallVector< ISD::ArgFlagsTy, 16 > OutFlags

SmallVector< Value *, 16 > OutVals

SmallVector< Register, 16 > OutRegs

CallLoweringInfo & setTailCall(bool Value=true)

SmallVector< Register, 4 > InRegs

CallLoweringInfo & setIsPatchPoint(bool Value=true)

CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, const Value *Target, ArgListTy &&ArgsList, const CallBase &Call)

SmallVector< ISD::InputArg, 4 > Ins

InputArg - This struct carries flags and type information about a single incoming (formal) argument o...

static const unsigned NoArgIndex

Sentinel value for implicit machine-level input arguments.

This class contains a discriminated union of information about pointers in memory operands,...

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.