HexagonGenInsert.cpp Source File (original) (raw)

39#include

40#include

41#include

42#include

43#include

44#include

46#define DEBUG_TYPE "hexinsert"

48using namespace llvm;

52 cl::desc("Vreg# cutoff for insert generation."));

57 cl::desc("Vreg distance cutoff for insert "

58 "generation."));

63 cl::desc("Maximum size of OrderedRegisterList"));

66 cl::desc("Maximum size of IFMap"));

69 cl::desc("Enable timing of insert generation"));

72 cl::desc("Enable detailed timing of insert "

73 "generation"));

84#ifndef NDEBUG

86#else

87 return false;

88#endif

89}

91namespace {

94 struct RegisterSet : private BitVector {

96 explicit RegisterSet(unsigned s, bool t = false) : BitVector(s, t) {}

101

102 unsigned find_first() const {

105 return 0;

106 return x2v(First);

107 }

108

109 unsigned find_next(unsigned Prev) const {

111 if (Next < 0)

112 return 0;

113 return x2v(Next);

114 }

115

117 unsigned Idx = v2x(R);

118 ensure(Idx);

120 }

122 unsigned Idx = v2x(R);

123 if (Idx >= size())

124 return *this;

126 }

127

130 }

133 }

134

135 reference operator[](unsigned R) {

136 unsigned Idx = v2x(R);

137 ensure(Idx);

139 }

140 bool operator[](unsigned R) const {

141 unsigned Idx = v2x(R);

144 }

145 bool has(unsigned R) const {

146 unsigned Idx = v2x(R);

147 if (Idx >= size())

148 return false;

150 }

151

152 bool empty() const {

154 }

156 return Rs.BitVector::subsetOf(*this);

157 }

160 }

161

162 private:

163 void ensure(unsigned Idx) {

164 if (size() <= Idx)

165 resize(std::max(Idx+1, 32U));

166 }

167

168 static inline unsigned v2x(unsigned v) {

169 return Register(v).virtRegIndex();

170 }

171

172 static inline unsigned x2v(unsigned x) {

173 return Register::index2VirtReg(x);

174 }

175 };

176

177 struct PrintRegSet {

178 PrintRegSet(const RegisterSet &S, const TargetRegisterInfo *RI)

179 : RS(S), TRI(RI) {}

180

181 friend raw_ostream &operator<< (raw_ostream &OS,

182 const PrintRegSet &P);

183

184 private:

186 const TargetRegisterInfo *TRI;

187 };

188

190 OS << '{';

191 for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))

193 OS << " }";

194 return OS;

195 }

196

197

198

199 struct UnsignedMap : public DenseMap<unsigned,unsigned> {

200 UnsignedMap() = default;

201

202 private:

203 using BaseType = DenseMap<unsigned, unsigned>;

204 };

205

206

207

208

209

210

211 struct RegisterOrdering : public UnsignedMap {

212 RegisterOrdering() = default;

213

214 unsigned operator[](unsigned VR) const {

215 const_iterator F = find(VR);

217 return F->second;

218 }

219

220

221

222 bool operator() (unsigned VR1, unsigned VR2) const {

223 return operator[](VR1) < operator[](VR2);

224 }

225 };

226

227

228

229

230

231

232

233 struct BitValueOrdering {

234 BitValueOrdering(const RegisterOrdering &RB) : BaseOrd(RB) {}

235

236 bool operator() (const BitTracker::BitValue &V1,

237 const BitTracker::BitValue &V2) const;

238

239 const RegisterOrdering &BaseOrd;

240 };

241

242}

243

246 if (V1 == V2)

247 return false;

248

249 if (V1.is(0) || V2.is(0))

250 return V1.is(0);

251

252

253 if (V2.is(1) || V1.is(1))

254 return !V2.is(1);

255

256 unsigned Ind1 = BaseOrd[V1.RefI.Reg], Ind2 = BaseOrd[V2.RefI.Reg];

257 if (Ind1 != Ind2)

258 return Ind1 < Ind2;

259

262}

263

264namespace {

265

266

267

268

269 struct CellMapShadow {

270 CellMapShadow(const BitTracker &T) : BT(T) {}

271

272 const BitTracker::RegisterCell &lookup(unsigned VR) {

273 unsigned RInd = Register(VR).virtRegIndex();

274

275 if (RInd >= CVect.size())

276 CVect.resize(std::max(RInd+16, 32U), nullptr);

277 const BitTracker::RegisterCell *CP = CVect[RInd];

278 if (CP == nullptr)

280 return *CP;

281 }

282

283 const BitTracker &BT;

284

285 private:

286 using CellVectType = std::vector<const BitTracker::RegisterCell *>;

287

288 CellVectType CVect;

289 };

290

291

292

293 struct RegisterCellLexCompare {

294 RegisterCellLexCompare(const BitValueOrdering &BO, CellMapShadow &M)

295 : BitOrd(BO), CM(M) {}

296

297 bool operator() (unsigned VR1, unsigned VR2) const;

298

299 private:

300 const BitValueOrdering &BitOrd;

301 CellMapShadow &CM;

302 };

303

304

305

306

307

308

309

310 struct RegisterCellBitCompareSel {

311 RegisterCellBitCompareSel(unsigned R, unsigned B, unsigned N,

312 const BitValueOrdering &BO, CellMapShadow &M)

313 : SelR(R), SelB(B), BitN(N), BitOrd(BO), CM(M) {}

314

315 bool operator() (unsigned VR1, unsigned VR2) const;

316

317 private:

318 const unsigned SelR, SelB;

319 const unsigned BitN;

320 const BitValueOrdering &BitOrd;

321 CellMapShadow &CM;

322 };

323

324}

325

326bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const {

327

328

329

330

331

332

333

334

335

336 if (VR1 == VR2)

337 return false;

338

339 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2);

340 uint16_t W1 = RC1.width(), W2 = RC2.width();

341 for (uint16_t i = 0, w = std::min(W1, W2); i < w; ++i) {

342 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i];

343 if (V1 != V2)

344 return BitOrd(V1, V2);

345 }

346

347 if (W1 != W2)

348 return W1 < W2;

349

350 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2];

351}

352

353bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const {

354 if (VR1 == VR2)

355 return false;

356 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1);

357 const BitTracker::RegisterCell &RC2 = CM.lookup(VR2);

358 uint16_t W1 = RC1.width(), W2 = RC2.width();

359 uint16_t Bit1 = (VR1 == SelR) ? SelB : BitN;

360 uint16_t Bit2 = (VR2 == SelR) ? SelB : BitN;

361

362

363

364

365

366 if (W1 <= Bit1)

367 return Bit2 < W2;

368

369 if (W2 <= Bit2)

370 return false;

371

372 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2];

373 if (V1 != V2)

374 return BitOrd(V1, V2);

375 return false;

376}

377

378namespace {

379

380 class OrderedRegisterList {

381 using ListType = std::vector;

382 const unsigned MaxSize;

383

384 public:

385 OrderedRegisterList(const RegisterOrdering &RO)

387

388 void insert(unsigned VR);

389 void remove(unsigned VR);

390

391 unsigned operator[](unsigned Idx) const {

392 assert(Idx < Seq.size());

393 return Seq[Idx];

394 }

395

396 unsigned size() const {

397 return Seq.size();

398 }

399

400 using iterator = ListType::iterator;

401 using const_iterator = ListType::const_iterator;

402

403 iterator begin() { return Seq.begin(); }

404 iterator end() { return Seq.end(); }

405 const_iterator begin() const { return Seq.begin(); }

406 const_iterator end() const { return Seq.end(); }

407

408

409 unsigned idx(iterator It) const { return It-begin(); }

410

411 private:

412 ListType Seq;

413 const RegisterOrdering &Ord;

414 };

415

416 struct PrintORL {

417 PrintORL(const OrderedRegisterList &L, const TargetRegisterInfo *RI)

418 : RL(L), TRI(RI) {}

419

420 friend raw_ostream &operator<< (raw_ostream &OS, const PrintORL &P);

421

422 private:

423 const OrderedRegisterList &RL;

424 const TargetRegisterInfo *TRI;

425 };

426

427 raw_ostream &operator<< (raw_ostream &OS, const PrintORL &P) {

428 OS << '(';

429 OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end();

430 for (OrderedRegisterList::const_iterator I = B; I != E; ++I) {

431 if (I != B)

432 OS << ", ";

434 }

435 OS << ')';

436 return OS;

437 }

438

439}

440

441void OrderedRegisterList::insert(unsigned VR) {

443 if (L == Seq.end())

444 Seq.push_back(VR);

445 else

446 Seq.insert(L, VR);

447

448 unsigned S = Seq.size();

449 if (S > MaxSize)

450 Seq.resize(MaxSize);

451 assert(Seq.size() <= MaxSize);

452}

453

454void OrderedRegisterList::remove(unsigned VR) {

456 if (L != Seq.end())

457 Seq.erase(L);

458}

459

460namespace {

461

462

463

464

465 struct IFRecord {

466 IFRecord(unsigned SR = 0, unsigned IR = 0, uint16_t W = 0, uint16_t O = 0)

467 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {}

468

469 unsigned SrcR, InsR;

470 uint16_t Wdh, Off;

471 };

472

473 struct PrintIFR {

474 PrintIFR(const IFRecord &R, const TargetRegisterInfo *RI)

475 : IFR(R), TRI(RI) {}

476

477 private:

478 friend raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P);

479

480 const IFRecord &IFR;

481 const TargetRegisterInfo *TRI;

482 };

483

484 raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) {

485 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;

487 << ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')';

488 return OS;

489 }

490

491 using IFRecordWithRegSet = std::pair<IFRecord, RegisterSet>;

492

493}

494

495namespace {

496

497 class HexagonGenInsert : public MachineFunctionPass {

498 public:

499 static char ID;

500

501 HexagonGenInsert() : MachineFunctionPass(ID) {}

502

503 StringRef getPassName() const override {

504 return "Hexagon generate \"insert\" instructions";

505 }

506

507 void getAnalysisUsage(AnalysisUsage &AU) const override {

508 AU.addRequired();

509 AU.addPreserved();

511 }

512

513 bool runOnMachineFunction(MachineFunction &MF) override;

514

515 private:

516 using PairMapType = DenseMap<std::pair<unsigned, unsigned>, unsigned>;

517

518 void buildOrderingMF(RegisterOrdering &RO) const;

519 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;

520 bool isIntClass(const TargetRegisterClass *RC) const;

522 bool isSmallConstant(unsigned VR) const;

523 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,

524 uint16_t L, uint16_t S) const;

525 bool findSelfReference(unsigned VR) const;

526 bool findNonSelfReference(unsigned VR) const;

527 void getInstrDefs(const MachineInstr *MI, RegisterSet &Defs) const;

528 void getInstrUses(const MachineInstr *MI, RegisterSet &Uses) const;

529 unsigned distance(const MachineBasicBlock *FromB,

530 const MachineBasicBlock *ToB, const UnsignedMap &RPO,

531 PairMapType &M) const;

534 PairMapType &M) const;

535 bool findRecordInsertForms(unsigned VR, OrderedRegisterList &AVs);

536 void collectInBlock(MachineBasicBlock *B, OrderedRegisterList &AVs);

537 void findRemovableRegisters(unsigned VR, IFRecord IF,

539 void computeRemovableRegisters();

540

541 void pruneEmptyLists();

542 void pruneCoveredSets(unsigned VR);

543 void pruneUsesTooFar(unsigned VR, const UnsignedMap &RPO, PairMapType &M);

544 void pruneRegCopies(unsigned VR);

545 void pruneCandidates();

546 void selectCandidates();

547 bool generateInserts();

548

550

551

552 using IFListType = std::vector;

553 using IFMapType = DenseMap<unsigned, IFListType>;

554

555 void dump_map() const;

556

557 const HexagonInstrInfo *HII = nullptr;

558 const HexagonRegisterInfo *HRI = nullptr;

559

560 MachineFunction *MFN;

561 MachineRegisterInfo *MRI;

562 MachineDominatorTree *MDT;

563 CellMapShadow *CMS;

564

565 RegisterOrdering BaseOrd;

566 RegisterOrdering CellOrd;

567 IFMapType IFMap;

568 };

569

570}

571

572char HexagonGenInsert::ID = 0;

573

574void HexagonGenInsert::dump_map() const {

575 for (const auto &I : IFMap) {

576 dbgs() << " " << printReg(I.first, HRI) << ":\n";

577 const IFListType &LL = I.second;

578 for (const auto &J : LL)

579 dbgs() << " " << PrintIFR(J.first, HRI) << ", "

580 << PrintRegSet(J.second, HRI) << '\n';

581 }

582}

583

584void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {

585 unsigned Index = 0;

586

587 for (const MachineBasicBlock &B : *MFN) {

589 continue;

590

591 for (const MachineInstr &MI : B) {

592 for (const MachineOperand &MO : MI.operands()) {

593 if (MO.isReg() && MO.isDef()) {

595 assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");

596 if (R.isVirtual())

597 RO.insert(std::make_pair(R, Index++));

598 }

599 }

600 }

601 }

602

603

604

605}

606

607void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,

608 RegisterOrdering &RO) const {

609

610

611 BitValueOrdering BVO(RB);

612 RegisterCellLexCompare LexCmp(BVO, *CMS);

613

614 using SortableVectorType = std::vector;

615

616 SortableVectorType VRs;

617 for (auto &I : RB)

618 VRs.push_back(I.first);

620

621 for (unsigned i = 0, n = VRs.size(); i < n; ++i)

622 RO.insert(std::make_pair(VRs[i], i));

623}

624

625inline bool HexagonGenInsert::isIntClass(const TargetRegisterClass *RC) const {

626 return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;

627}

628

629bool HexagonGenInsert::isConstant(unsigned VR) const {

630 const BitTracker::RegisterCell &RC = CMS->lookup(VR);

631 uint16_t W = RC.width();

632 for (uint16_t i = 0; i < W; ++i) {

633 const BitTracker::BitValue &BV = RC[i];

634 if (BV.is(0) || BV.is(1))

635 continue;

636 return false;

637 }

638 return true;

639}

640

641bool HexagonGenInsert::isSmallConstant(unsigned VR) const {

642 const BitTracker::RegisterCell &RC = CMS->lookup(VR);

643 uint16_t W = RC.width();

644 if (W > 64)

645 return false;

646 uint64_t V = 0, B = 1;

647 for (uint16_t i = 0; i < W; ++i) {

648 const BitTracker::BitValue &BV = RC[i];

649 if (BV.is(1))

650 V |= B;

651 else if (!BV.is(0))

652 return false;

653 B <<= 1;

654 }

655

656

657 if (W == 32)

659

660

662}

663

664bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR,

665 unsigned InsR, uint16_t L, uint16_t S) const {

666 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);

667 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);

668 const TargetRegisterClass *InsRC = MRI->getRegClass(InsR);

669

670 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))

671 return false;

672

673 if (DstRC != SrcRC)

674 return false;

675 if (DstRC == InsRC)

676 return true;

677

678 if (DstRC == &Hexagon::DoubleRegsRegClass)

679 return false;

680

681 if (S < 32 && S+L > 32)

682 return false;

683 return true;

684}

685

686bool HexagonGenInsert::findSelfReference(unsigned VR) const {

687 const BitTracker::RegisterCell &RC = CMS->lookup(VR);

688 for (uint16_t i = 0, w = RC.width(); i < w; ++i) {

689 const BitTracker::BitValue &V = RC[i];

691 return true;

692 }

693 return false;

694}

695

696bool HexagonGenInsert::findNonSelfReference(unsigned VR) const {

697 BitTracker::RegisterCell RC = CMS->lookup(VR);

698 for (uint16_t i = 0, w = RC.width(); i < w; ++i) {

699 const BitTracker::BitValue &V = RC[i];

701 return true;

702 }

703 return false;

704}

705

706void HexagonGenInsert::getInstrDefs(const MachineInstr *MI,

708 for (const MachineOperand &MO : MI->operands()) {

709 if (!MO.isReg() || !MO.isDef())

710 continue;

712 if (.isVirtual())

713 continue;

714 Defs.insert(R);

715 }

716}

717

718void HexagonGenInsert::getInstrUses(const MachineInstr *MI,

720 for (const MachineOperand &MO : MI->operands()) {

721 if (!MO.isReg() || !MO.isUse())

722 continue;

724 if (.isVirtual())

725 continue;

726 Uses.insert(R);

727 }

728}

729

730unsigned HexagonGenInsert::distance(const MachineBasicBlock *FromB,

731 const MachineBasicBlock *ToB, const UnsignedMap &RPO,

732 PairMapType &M) const {

733

734

735 assert(FromB != ToB);

736

738

739 PairMapType::iterator F = M.find(std::make_pair(FromN, ToN));

740 if (F != M.end())

741 return F->second;

742 unsigned ToRPO = RPO.lookup(ToN);

743

744 unsigned MaxD = 0;

745

746 for (const MachineBasicBlock *PB : ToB->predecessors()) {

747

748

749

750 if (PB == FromB || RPO.lookup(PB->getNumber()) >= ToRPO)

751 continue;

752 unsigned D = PB->size() + distance(FromB, PB, RPO, M);

753 if (D > MaxD)

754 MaxD = D;

755 }

756

757

758 M.insert(std::make_pair(std::make_pair(FromN, ToN), MaxD));

759 return MaxD;

760}

761

764 PairMapType &M) const {

765 const MachineBasicBlock *FB = FromI->getParent(), *TB = ToI->getParent();

766 if (FB == TB)

767 return std::distance(FromI, ToI);

768 unsigned D1 = std::distance(TB->begin(), ToI);

769 unsigned D2 = distance(FB, TB, RPO, M);

770 unsigned D3 = std::distance(FromI, FB->end());

771 return D1+D2+D3;

772}

773

774bool HexagonGenInsert::findRecordInsertForms(unsigned VR,

775 OrderedRegisterList &AVs) {

777 dbgs() << __func__ << ": " << printReg(VR, HRI)

778 << " AVs: " << PrintORL(AVs, HRI) << "\n";

779 }

780 if (AVs.size() == 0)

781 return false;

782

783 using iterator = OrderedRegisterList::iterator;

784

785 BitValueOrdering BVO(BaseOrd);

786 const BitTracker::RegisterCell &RC = CMS->lookup(VR);

787 uint16_t W = RC.width();

788

789 using RSRecord = std::pair<unsigned, uint16_t>;

790 using RSListType = std::vector;

791

792

793

794 using LRSMapType = DenseMap<unsigned, RSListType>;

795 LRSMapType LM;

796

797

798

799

800 for (uint16_t S = 0; S < W; ++S) {

801 iterator B = AVs.begin(), E = AVs.end();

802

803

804

805

806

807

808 uint16_t L;

809 for (L = 0; L < W-S; ++L) {

810

811

812 RegisterCellBitCompareSel RCB(VR, S+L, L, BVO, *CMS);

813 iterator NewB = std::lower_bound(B, E, VR, RCB);

814 iterator NewE = std::upper_bound(NewB, E, VR, RCB);

815

816

817

818

819 if (L > 0) {

820 for (iterator I = B; I != NewB; ++I)

821 LM[L].push_back(std::make_pair(*I, S));

822 for (iterator I = NewE; I != E; ++I)

823 LM[L].push_back(std::make_pair(*I, S));

824 }

825 B = NewB, E = NewE;

826 if (B == E)

827 break;

828 }

829

830

832 if (B != E) {

833 for (iterator I = B; I != E; ++I)

834 LM[L].push_back(std::make_pair(*I, S));

835

836

837 break;

838 }

839 }

840

842 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";

843 for (const auto &I : LM) {

844 dbgs() << " L=" << I.first << ':';

845 const RSListType &LL = I.second;

846 for (const auto &J : LL)

847 dbgs() << " (" << printReg(J.first, HRI) << ",@" << J.second << ')';

848 dbgs() << '\n';

849 }

850 }

851

852 bool Recorded = false;

853

854 for (unsigned SrcR : AVs) {

855 int FDi = -1, LDi = -1;

856 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR);

857 uint16_t AW = AC.width();

858 for (uint16_t i = 0, w = std::min(W, AW); i < w; ++i) {

859 if (RC[i] == AC[i])

860 continue;

861 if (FDi == -1)

862 FDi = i;

863 LDi = i;

864 }

865 if (FDi == -1)

866 continue;

867

868

869 uint16_t FD = FDi, LD = LDi;

870 uint16_t MinL = LD-FD+1;

871 for (uint16_t L = MinL; L < W; ++L) {

872 LRSMapType::iterator F = LM.find(L);

873 if (F == LM.end())

874 continue;

875 RSListType &LL = F->second;

876 for (const auto &I : LL) {

877 uint16_t S = I.second;

878

879

880

881

882 if (S > FD)

883 continue;

884 uint16_t EL = L-MinL;

885 uint16_t LowS = (EL < FD) ? FD-EL : 0;

886 if (S < LowS)

887 continue;

888 unsigned InsR = I.first;

889 if (!isValidInsertForm(VR, SrcR, InsR, L, S))

890 continue;

893 << ',' << printReg(InsR, HRI) << ",#" << L << ",#"

894 << S << ")\n";

895 }

896 IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet());

897 IFMap[VR].push_back(RR);

898 Recorded = true;

899 }

900 }

901 }

902

903 return Recorded;

904}

905

906void HexagonGenInsert::collectInBlock(MachineBasicBlock *B,

907 OrderedRegisterList &AVs) {

910

911

912

914 return;

915

917

918

919

921 for (MachineInstr &MI : *B) {

922

924 break;

925

926 InsDefs.clear();

927 getInstrDefs(&MI, InsDefs);

928

929 bool Skip = MI.isCopy() || MI.isRegSequence();

930

931 if (!Skip) {

932

933

934 for (unsigned VR = InsDefs.find_first(); VR; VR = InsDefs.find_next(VR)) {

935

936

938 continue;

939

940

941

942

943 if (findSelfReference(VR) || isSmallConstant(VR))

944 continue;

945

946 findRecordInsertForms(VR, AVs);

947

949 break;

950 }

951 }

952

953

954

955 for (unsigned VR = InsDefs.find_first(); VR; VR = InsDefs.find_next(VR))

956 AVs.insert(VR);

957 BlockDefs.insert(InsDefs);

958 }

959

961 MachineBasicBlock *SB = DTN->getBlock();

962 collectInBlock(SB, AVs);

963 }

964

965 for (unsigned VR = BlockDefs.find_first(); VR; VR = BlockDefs.find_next(VR))

966 AVs.remove(VR);

967}

968

969void HexagonGenInsert::findRemovableRegisters(unsigned VR, IFRecord IF,

971

972

973

974

976

977 unsigned S = 0;

978 Regs[S].insert(VR);

979

980 while (!Regs[S].empty()) {

981

982 unsigned OtherS = 1-S;

983 Regs[OtherS].clear();

984 for (unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) {

985 Regs[S].remove(R);

986 if (R == IF.SrcR || R == IF.InsR)

987 continue;

988

989

990

991

992

993

994

995

996

997

998 if (!findNonSelfReference(R))

999 continue;

1000 RMs.insert(R);

1001 const MachineInstr *DefI = MRI->getVRegDef(R);

1003

1004

1005

1006 if (DefI->isPHI())

1007 continue;

1008 getInstrUses(DefI, Regs[OtherS]);

1009 }

1010 S = OtherS;

1011 }

1012

1013

1014

1015

1016

1017 RMs.remove(VR);

1018}

1019

1020void HexagonGenInsert::computeRemovableRegisters() {

1021 for (auto &I : IFMap) {

1022 IFListType &LL = I.second;

1023 for (auto &J : LL)

1024 findRemovableRegisters(I.first, J.first, J.second);

1025 }

1026}

1027

1028void HexagonGenInsert::pruneEmptyLists() {

1029

1030

1032 IterListType Prune;

1033 for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {

1034 if (I->second.empty())

1035 Prune.push_back(I);

1036 }

1037 for (const auto &It : Prune)

1038 IFMap.erase(It);

1039}

1040

1041void HexagonGenInsert::pruneCoveredSets(unsigned VR) {

1042 IFMapType::iterator F = IFMap.find(VR);

1043 assert(F != IFMap.end());

1044 IFListType &LL = F->second;

1045

1046

1047

1048

1049

1050

1051

1052

1053 MachineInstr *DefVR = MRI->getVRegDef(VR);

1055 bool HasNE = false;

1056 for (const auto &I : LL) {

1057 if (I.second.empty())

1058 continue;

1059 HasNE = true;

1060 break;

1061 }

1062 if (!DefEx || HasNE) {

1063

1064

1065 auto IsEmpty = [] (const IFRecordWithRegSet &IR) -> bool {

1066 return IR.second.empty();

1067 };

1069 } else {

1070

1071

1072

1073

1074

1075 IFRecord MaxIF = LL[0].first;

1076 for (unsigned i = 1, n = LL.size(); i < n; ++i) {

1077

1078 const IFRecord &IF = LL[i].first;

1079 unsigned M0 = BaseOrd[MaxIF.SrcR], M1 = BaseOrd[MaxIF.InsR];

1080 unsigned R0 = BaseOrd[IF.SrcR], R1 = BaseOrd[IF.InsR];

1081 if (M0 > R0)

1082 continue;

1083 if (M0 == R0) {

1084 if (M1 > R1)

1085 continue;

1086 if (M1 == R1) {

1087 if (MaxIF.Wdh > IF.Wdh)

1088 continue;

1089 if (MaxIF.Wdh == IF.Wdh && MaxIF.Off >= IF.Off)

1090 continue;

1091 }

1092 }

1093

1094 MaxIF = IF;

1095 }

1096

1097

1098 LL.clear();

1099 LL.push_back(std::make_pair(MaxIF, RegisterSet()));

1100 }

1101

1102

1103

1104

1105

1106

1107

1108

1109 for (unsigned i = 0, n = LL.size(); i < n; ) {

1111 unsigned j = 0;

1112 while (j < n) {

1113 if (j != i && LL[j].second.includes(RMi))

1114 break;

1115 j++;

1116 }

1117 if (j == n) {

1118 i++;

1119 continue;

1120 }

1121 LL.erase(LL.begin()+i);

1122 n = LL.size();

1123 }

1124}

1125

1126void HexagonGenInsert::pruneUsesTooFar(unsigned VR, const UnsignedMap &RPO,

1127 PairMapType &M) {

1128 IFMapType::iterator F = IFMap.find(VR);

1129 assert(F != IFMap.end());

1130 IFListType &LL = F->second;

1132 const MachineInstr *DefV = MRI->getVRegDef(VR);

1133

1134 for (unsigned i = LL.size(); i > 0; --i) {

1135 unsigned SR = LL[i-1].first.SrcR, IR = LL[i-1].first.InsR;

1136 const MachineInstr *DefS = MRI->getVRegDef(SR);

1137 const MachineInstr *DefI = MRI->getVRegDef(IR);

1138 unsigned DSV = distance(DefS, DefV, RPO, M);

1139 if (DSV < Cutoff) {

1140 unsigned DIV = distance(DefI, DefV, RPO, M);

1141 if (DIV < Cutoff)

1142 continue;

1143 }

1144 LL.erase(LL.begin()+(i-1));

1145 }

1146}

1147

1148void HexagonGenInsert::pruneRegCopies(unsigned VR) {

1149 IFMapType::iterator F = IFMap.find(VR);

1150 assert(F != IFMap.end());

1151 IFListType &LL = F->second;

1152

1153 auto IsCopy = [] (const IFRecordWithRegSet &IR) -> bool {

1154 return IR.first.Wdh == 32 && (IR.first.Off == 0 || IR.first.Off == 32);

1155 };

1157}

1158

1159void HexagonGenInsert::pruneCandidates() {

1160

1161

1162

1163

1164 for (const auto &I : IFMap)

1165 pruneCoveredSets(I.first);

1166

1167 UnsignedMap RPO;

1168

1169 using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;

1170

1171 RPOTType RPOT(MFN);

1172 unsigned RPON = 0;

1173 for (const auto &I : RPOT)

1174 RPO[I->getNumber()] = RPON++;

1175

1176 PairMapType Memo;

1177

1178 for (const auto &I : IFMap)

1179 pruneUsesTooFar(I.first, RPO, Memo);

1180

1181 pruneEmptyLists();

1182

1183 for (const auto &I : IFMap)

1184 pruneRegCopies(I.first);

1185}

1186

1187namespace {

1188

1189

1190

1191

1192

1193

1194

1195

1196

1197 struct IFOrdering {

1198 IFOrdering(const UnsignedMap &UC, const RegisterOrdering &BO)

1199 : UseC(UC), BaseOrd(BO) {}

1200

1201 bool operator() (const IFRecordWithRegSet &A,

1202 const IFRecordWithRegSet &B) const;

1203

1204 private:

1206 unsigned &Sum) const;

1207

1208 const UnsignedMap &UseC;

1209 const RegisterOrdering &BaseOrd;

1210 };

1211

1212}

1213

1214bool IFOrdering::operator() (const IFRecordWithRegSet &A,

1215 const IFRecordWithRegSet &B) const {

1216 unsigned SizeA = 0, ZeroA = 0, SumA = 0;

1217 unsigned SizeB = 0, ZeroB = 0, SumB = 0;

1218 stats(A.second, SizeA, ZeroA, SumA);

1219 stats(B.second, SizeB, ZeroB, SumB);

1220

1221

1222 if (ZeroA != ZeroB)

1223 return ZeroA > ZeroB;

1224

1225 uint64_t AvgA = SumA*SizeB, AvgB = SumB*SizeA;

1226 if (AvgA != AvgB)

1227 return AvgA < AvgB;

1228

1229

1230

1231 unsigned OSA = BaseOrd[A.first.SrcR], OSB = BaseOrd[B.first.SrcR];

1232 if (OSA != OSB)

1233 return OSA < OSB;

1234 unsigned OIA = BaseOrd[A.first.InsR], OIB = BaseOrd[B.first.InsR];

1235 if (OIA != OIB)

1236 return OIA < OIB;

1237 if (A.first.Wdh != B.first.Wdh)

1238 return A.first.Wdh < B.first.Wdh;

1239 return A.first.Off < B.first.Off;

1240}

1241

1242void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,

1243 unsigned &Sum) const {

1244 for (unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) {

1245 UnsignedMap::const_iterator F = UseC.find(R);

1246 assert(F != UseC.end());

1247 unsigned UC = F->second;

1248 if (UC == 0)

1250 Sum += UC;

1252 }

1253}

1254

1255void HexagonGenInsert::selectCandidates() {

1256

1257

1258

1259

1260

1261

1263 UnsignedMap UseC, RemC;

1264 IFMapType::iterator End = IFMap.end();

1265

1266 for (IFMapType::iterator I = IFMap.begin(); I != End; ++I) {

1267 const IFListType &LL = I->second;

1269 for (const auto &J : LL)

1270 TT.insert(J.second);

1271 for (unsigned R = TT.find_first(); R; R = TT.find_next(R))

1272 RemC[R]++;

1273 AllRMs.insert(TT);

1274 }

1275

1276 for (unsigned R = AllRMs.find_first(); R; R = AllRMs.find_next(R)) {

1278 using InstrSet = SmallPtrSet<const MachineInstr *, 16>;

1279

1280 InstrSet UIs;

1281

1282

1283 use_iterator E = MRI->use_nodbg_end();

1284 for (use_iterator I = MRI->use_nodbg_begin(R); I != E; ++I)

1285 UIs.insert(I->getParent());

1286 unsigned C = UIs.size();

1287

1288

1289 unsigned D = RemC[R];

1290 UseC[R] = (C > D) ? C-D : 0;

1291 }

1292

1294 if (!SelectAll0 && !SelectHas0)

1295 SelectAll0 = true;

1296

1297

1298

1299

1300

1301

1302 IFOrdering IFO(UseC, BaseOrd);

1303 for (IFMapType::iterator I = IFMap.begin(); I != End; ++I) {

1304 IFListType &LL = I->second;

1305 if (LL.empty())

1306 continue;

1307

1308

1309

1310

1312 assert(MinI != LL.end());

1313 IFRecordWithRegSet M = *MinI;

1314 LL.clear();

1315

1316

1317

1318

1319

1320

1321

1323 const MachineInstr *DefI = MRI->getVRegDef(I->first);

1324 getInstrUses(DefI, Us);

1325 bool Accept = false;

1326

1327 if (SelectAll0) {

1328 bool All0 = true;

1329 for (unsigned R = Us.find_first(); R; R = Us.find_next(R)) {

1330 if (UseC[R] == 0)

1331 continue;

1332 All0 = false;

1333 break;

1334 }

1335 Accept = All0;

1336 } else if (SelectHas0) {

1337 bool Has0 = false;

1338 for (unsigned R = Us.find_first(); R; R = Us.find_next(R)) {

1339 if (UseC[R] != 0)

1340 continue;

1341 Has0 = true;

1342 break;

1343 }

1344 Accept = Has0;

1345 }

1346 if (Accept)

1347 LL.push_back(M);

1348 }

1349

1350

1351

1352

1353

1354 AllRMs.clear();

1355 for (IFMapType::iterator I = IFMap.begin(); I != End; ++I) {

1356 const IFListType &LL = I->second;

1357 if (!LL.empty())

1358 AllRMs.insert(LL[0].second);

1359 }

1360 for (IFMapType::iterator I = IFMap.begin(); I != End; ++I) {

1361 IFListType &LL = I->second;

1362 if (LL.empty())

1363 continue;

1364 unsigned SR = LL[0].first.SrcR, IR = LL[0].first.InsR;

1365 if (AllRMs[SR] || AllRMs[IR])

1366 LL.clear();

1367 }

1368

1369 pruneEmptyLists();

1370}

1371

1372bool HexagonGenInsert::generateInserts() {

1373

1374

1375 UnsignedMap RegMap;

1376 for (auto &I : IFMap) {

1377 unsigned VR = I.first;

1378 const TargetRegisterClass *RC = MRI->getRegClass(VR);

1379 Register NewVR = MRI->createVirtualRegister(RC);

1380 RegMap[VR] = NewVR;

1381 }

1382

1383

1384

1385

1386 for (auto &I : IFMap) {

1387 MachineInstr *MI = MRI->getVRegDef(I.first);

1388 MachineBasicBlock &B = *MI->getParent();

1390 unsigned NewR = RegMap[I.first];

1391 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;

1392 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)

1393 : HII->get(Hexagon::S2_insertp);

1394 IFRecord IF = I.second[0].first;

1395 unsigned Wdh = IF.Wdh, Off = IF.Off;

1396 unsigned InsS = 0;

1397 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {

1398 InsS = Hexagon::isub_lo;

1399 if (Off >= 32) {

1400 InsS = Hexagon::isub_hi;

1401 Off -= 32;

1402 }

1403 }

1404

1405

1407 if (MI->isPHI())

1408 At = B.getFirstNonPHI();

1409

1412 .addReg(IF.InsR, 0, InsS)

1415

1416 MRI->clearKillFlags(IF.SrcR);

1417 MRI->clearKillFlags(IF.InsR);

1418 }

1419

1420 for (const auto &I : IFMap) {

1421 MachineInstr *DefI = MRI->getVRegDef(I.first);

1422 MRI->replaceRegWith(I.first, RegMap[I.first]);

1424 }

1425

1426 return true;

1427}

1428

1431

1433 Changed |= removeDeadCode(DTN);

1434

1435 MachineBasicBlock *B = N->getBlock();

1436 std::vector<MachineInstr*> Instrs;

1438 Instrs.push_back(&MI);

1439

1440 for (MachineInstr *MI : Instrs) {

1441 unsigned Opc = MI->getOpcode();

1442

1443

1444 if (Opc == TargetOpcode::LIFETIME_START ||

1445 Opc == TargetOpcode::LIFETIME_END)

1446 continue;

1447 bool Store = false;

1448 if (MI->isInlineAsm() || ->isSafeToMove(Store))

1449 continue;

1450

1451 bool AllDead = true;

1452 SmallVector<unsigned,2> Regs;

1453 for (const MachineOperand &MO : MI->operands()) {

1454 if (!MO.isReg() || !MO.isDef())

1455 continue;

1457 if (.isVirtual() || MRI ->use_nodbg_empty(R)) {

1458 AllDead = false;

1459 break;

1460 }

1462 }

1463 if (!AllDead)

1464 continue;

1465

1466 B->erase(MI);

1467 for (unsigned Reg : Regs)

1468 MRI->markUsesInDebugValueAsUndef(Reg);

1470 }

1471

1473}

1474

1475bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {

1477 return false;

1478

1481

1482

1484

1485 IFMap.clear();

1486 BaseOrd.clear();

1487 CellOrd.clear();

1488

1489 const auto &ST = MF.getSubtarget();

1490 HII = ST.getInstrInfo();

1491 HRI = ST.getRegisterInfo();

1492 MFN = &MF;

1494 MDT = &getAnalysis().getDomTree();

1495

1496

1497

1498

1499

1500

1502

1503 const HexagonEvaluator HE(*HRI, *MRI, *HII, MF);

1504 BitTracker BTLoc(HE, MF);

1506 BTLoc.run();

1507 CellMapShadow MS(BTLoc);

1508 CMS = &MS;

1509

1510 buildOrderingMF(BaseOrd);

1511 buildOrderingBT(BaseOrd, CellOrd);

1512

1514 dbgs() << "Cell ordering:\n";

1515 for (const auto &I : CellOrd) {

1516 unsigned VR = I.first, Pos = I.second;

1517 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";

1518 }

1519 }

1520

1521

1522 MachineBasicBlock *RootB = MDT->getRoot();

1523 OrderedRegisterList AvailR(CellOrd);

1524

1525 const char *const TGName = "hexinsert";

1526 const char *const TGDesc = "Generate Insert Instructions";

1527

1528 {

1529 NamedRegionTimer _T("collection", "collection", TGName, TGDesc,

1530 TimingDetail);

1531 collectInBlock(RootB, AvailR);

1532

1533 computeRemovableRegisters();

1534 }

1535

1537 dbgs() << "Candidates after collection:\n";

1538 dump_map();

1539 }

1540

1541 if (IFMap.empty())

1543

1544 {

1545 NamedRegionTimer _T("pruning", "pruning", TGName, TGDesc, TimingDetail);

1546 pruneCandidates();

1547 }

1548

1550 dbgs() << "Candidates after pruning:\n";

1551 dump_map();

1552 }

1553

1554 if (IFMap.empty())

1556

1557 {

1558 NamedRegionTimer _T("selection", "selection", TGName, TGDesc, TimingDetail);

1559 selectCandidates();

1560 }

1561

1563 dbgs() << "Candidates after selection:\n";

1564 dump_map();

1565 }

1566

1567

1570

1572

1573 IterListType Out;

1574 for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {

1575 unsigned Idx = Register(I->first).virtRegIndex();

1576 if (Idx >= Cutoff)

1577 Out.push_back(I);

1578 }

1579 for (const auto &It : Out)

1580 IFMap.erase(It);

1581 }

1582 if (IFMap.empty())

1584

1585 {

1586 NamedRegionTimer _T("generation", "generation", TGName, TGDesc,

1587 TimingDetail);

1588 generateInserts();

1589 }

1590

1591 return true;

1592}

1593

1595 return new HexagonGenInsert();

1596}

1597

1598

1599

1600

1601

1603 "Hexagon generate \"insert\" instructions", false, false)

1606 "Hexagon generate \"insert\" instructions", false, false)

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isConstant(const MachineInstr &MI)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file implements the BitVector class.

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

static std::optional< ArrayRef< InsnRange >::iterator > intersects(const MachineInstr *StartMI, const MachineInstr *EndMI, ArrayRef< InsnRange > Ranges, const InstructionOrdering &Ordering)

Check if the instruction range [StartMI, EndMI] intersects any instruction range in Ranges.

This file defines the DenseMap class.

This file defines the little GraphTraits template class that should be specialized by classes that...

static cl::opt< bool > OptConst("insert-const", cl::init(false), cl::Hidden)

static bool isDebug()

Definition HexagonGenInsert.cpp:83

static cl::opt< unsigned > MaxORLSize("insert-max-orl", cl::init(4096), cl::Hidden, cl::desc("Maximum size of OrderedRegisterList"))

static cl::opt< unsigned > MaxIFMSize("insert-max-ifmap", cl::init(1024), cl::Hidden, cl::desc("Maximum size of IFMap"))

static cl::opt< bool > OptTimingDetail("insert-timing-detail", cl::Hidden, cl::desc("Enable detailed timing of insert " "generation"))

static cl::opt< bool > OptTiming("insert-timing", cl::Hidden, cl::desc("Enable timing of insert generation"))

static cl::opt< unsigned > VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden, cl::desc("Vreg distance cutoff for insert " "generation."))

static cl::opt< bool > OptSelectAll0("insert-all0", cl::init(false), cl::Hidden)

static cl::opt< unsigned > VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, cl::desc("Vreg# cutoff for insert generation."))

static cl::opt< bool > OptSelectHas0("insert-has0", cl::init(false), cl::Hidden)

static bool lookup(const GsymReader &GR, DataExtractor &Data, uint64_t &Offset, uint64_t BaseAddr, uint64_t Addr, SourceLocations &SrcLocs, llvm::Error &Err)

A Lookup helper functions.

Legalize the Machine IR a function s Machine IR

Promote Memory to Register

PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.

Remove Loads Into Fake Uses

This file defines the SmallVector class.

SmallSet< unsigned, 4 > RegisterSet

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

bool test(unsigned Idx) const

int find_first() const

find_first - Returns the index of the first set bit, -1 if none of the bits are set.

bool anyCommon(const BitVector &RHS) const

Test if any common bits are set.

bool any() const

any - Returns true if any bit is set.

BitVector & operator|=(const BitVector &RHS)

int find_next(unsigned Prev) const

find_next - Returns the index of the next set bit following the "Prev" bit.

reference operator[](unsigned Idx)

DomTreeNodeBase< NodeT > * getRootNode()

getRootNode - This returns the entry node for the CFG of the function.

DomTreeNodeBase< NodeT > * getNode(const NodeT *BB) const

getNode - return the (Post)DominatorTree node for the specified basic block.

FunctionPass class - This class is used to implement most global optimizations.

bool isConstExtended(const MachineInstr &MI) const

MachineInstrBundleIterator< const MachineInstr > const_iterator

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

iterator_range< pred_iterator > predecessors()

MachineInstrBundleIterator< MachineInstr > iterator

Analysis pass which computes a MachineDominatorTree.

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

defusechain_iterator< true, false, true, true, false > use_nodbg_iterator

use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...

SmallSet & operator=(const SmallSet &)=default

const_iterator end() const

std::pair< const_iterator, bool > insert(const unsigned &V)

void push_back(const T &Elt)

This class implements an extremely fast bulk output stream that can only output to a stream.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

@ TB

TB - TwoByte - Set if this instruction has a two byte opcode, which starts with a 0x0F byte before th...

initializer< Ty > init(const Ty &Val)

LLVM_ABI iterator begin() const

LLVM_ABI std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)

Remove path.

This is an optimization pass for GlobalISel generic memory operations.

auto find(R &&Range, const T &Val)

Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.

bool includes(R1 &&Range1, R2 &&Range2)

Provide wrappers to std::includes which take ranges instead of having to pass begin/end explicitly.

auto min_element(R &&Range)

Provide wrappers to std::min_element which take ranges instead of having to pass begin/end explicitly...

auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)

Get the size of a range.

LLVM_ABI bool isCurrentDebugType(const char *Type, int Level=0)

isCurrentDebugType - Return true if the specified string is the debug type specified on the command l...

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

unsigned M1(unsigned Val)

LLVM_ABI bool DebugFlag

This boolean is set to true if the '-debug' command line option is specified.

auto reverse(ContainerTy &&C)

void sort(IteratorTy Start, IteratorTy End)

constexpr uint32_t Hi_32(uint64_t Value)

Return the high 32 bits of a 64 bit value.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

FunctionPass * createHexagonGenInsert()

Definition HexagonGenInsert.cpp:1594

constexpr uint32_t Lo_32(uint64_t Value)

Return the low 32 bits of a 64 bit value.

DomTreeNodeBase< MachineBasicBlock > MachineDomTreeNode

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

FunctionAddr VTableAddr Next

raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)

unsigned M0(unsigned Val)

void erase_if(Container &C, UnaryPredicate P)

Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...

iterator_range< typename GraphTraits< GraphType >::ChildIteratorType > children(const typename GraphTraits< GraphType >::NodeRef &G)

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)

Prints a machine basic block reference.

bool is(unsigned T) const

const RegisterCell & lookup(unsigned Reg) const

bool reached(const MachineBasicBlock *B) const