HexagonMCInstrInfo.cpp Source File (original) (raw)

29#include

30#include

31#include

33using namespace llvm;

36 return Register != Hexagon::NoRegister;

37}

41 : MCII(MCII), BundleCurrent(Inst.begin() +

43 BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}

46 MCInst const &Inst, std::nullptr_t)

47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),

48 DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}

51 if (DuplexCurrent != DuplexEnd) {

52 ++DuplexCurrent;

53 if (DuplexCurrent == DuplexEnd) {

54 DuplexCurrent = BundleEnd;

55 DuplexEnd = BundleEnd;

56 ++BundleCurrent;

57 }

58 return *this;

59 }

60 ++BundleCurrent;

61 if (BundleCurrent != BundleEnd) {

62 MCInst const &Inst = *BundleCurrent->getInst();

64 DuplexCurrent = Inst.begin();

65 DuplexEnd = Inst.end();

66 }

67 }

68 return *this;

69}

72 if (DuplexCurrent != DuplexEnd)

73 return *DuplexCurrent->getInst();

74 return *BundleCurrent->getInst();

75}

78 return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&

79 DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;

80}

85}

100}

101

108}

109

114}

115

119 else

120 return (1);

121}

122

123namespace {

127

128 bool CheckOk = Check ? Check->check(false) : true;

129 if (!CheckOk)

130 return false;

131

132 MCInst OrigMCB = MCB;

133

134

135

139

141 (STI.hasFeature(Hexagon::FeatureDuplex))

144

145

146

148

149

150

152

153

154

156 if (Check)

157 Check->reportError("invalid instruction packet: out of slots");

158 return false;

159 }

160

161 CheckOk = Check ? Check->check(true) : true;

162 if (!CheckOk)

163 return false;

164

166

167 return true;

168}

169}

170

175 bool AttemptCompatibility) {

177 if (!AttemptCompatibility || ArchSTI == nullptr)

178 return canonicalizePacketImpl(MCII, STI, Context, MCB, Check);

179

181 HexagonMCChecker DefaultCheck(Context, MCII, STI, MCB, *RI, false);

184 if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck))

185 return true;

186

188 return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck);

189}

190

196

201 else if (MO.isExpr())

203 else

205 return XMI;

206}

207

210 MCInst const &inst1) {

211 assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");

213 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);

214

219 return duplexInst;

220}

221

223 size_t Index) {

225 if (Index == 0)

226 return nullptr;

230 return Inst;

231 return nullptr;

232}

233

239}

240

246}

247

253}

254

258}

259

261 using namespace Hexagon;

262

263 switch (Reg.id()) {

264 default:

266

267 case R0:

268 case D0:

269 return 0;

270 case R1:

271 case D1:

272 return 1;

273 case R2:

274 case D2:

275 return 2;

276 case R3:

277 case D3:

278 return 3;

279 case R4:

280 case D8:

281 return 4;

282 case R5:

283 case D9:

284 return 5;

285 case R6:

286 case D10:

287 return 6;

288 case R7:

289 case D11:

290 return 7;

291 case R16:

292 return 8;

293 case R17:

294 return 9;

295 case R18:

296 return 10;

297 case R19:

298 return 11;

299 case R20:

300 return 12;

301 case R21:

302 return 13;

303 case R22:

304 return 14;

305 case R23:

306 return 15;

307 }

308}

309

311 const auto &HExpr = cast(Expr);

312 assert(HExpr.getExpr());

313 return *HExpr.getExpr();

314}

315

320}

321

327

331 return (MO);

332}

333

338}

339

344}

345

350}

351

352

357

361}

362

363

368

371 return 0;

372}

373

377}

378

383}

384

388

389

391 return (MCO);

392 } else {

395

399 return (MCO);

400 }

401}

402

403

408}

409

415

419 return (MCO);

420}

421

422

427}

428

429

433

436 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage;

437

438

439

440

441

442 unsigned Stage = II[SchedClass].LastStage - 1;

443

444 if (Size < 2)

445 return 0;

447}

448

449

456}

457

458

459

460

466 unsigned Slots = 0;

467

468

469

470

471 for (unsigned Stage = II[SchedClass].FirstStage + 1;

472 Stage < II[SchedClass].LastStage; ++Stage) {

475 break;

476

477 Slots |= Units;

478 }

479

480

481 return Slots;

482}

483

486 return false;

487

490 return true;

491 }

492

493 return false;

494}

495

498}

499

502 return false;

503

506 return true;

507 }

508

509 return false;

510}

511

512

517}

518

519

524}

525

530}

531

532

537}

538

540 auto Result = Hexagon::BUNDLE == MCI.getOpcode();

542 return Result;

543}

544

548 return true;

550 return false;

552 if (isa(MO.getExpr()) &&

554 return true;

555

561 return false;

562

564 (MCI.getOpcode() != Hexagon::C4_addipc))

565 return false;

566

568 if (isa(MO.getExpr()) &&

570 return false;

571

573 if (!MO.getExpr()->evaluateAsAbsolute(Value))

574 return true;

576 int32_t SValue = Value;

579 return SValue < MinValue || SValue > MaxValue;

580 }

584 return UValue < MinValue || UValue > MaxValue;

585}

586

590}

591

595}

596

601}

602

607}

608

612}

613

617}

618

620 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||

621 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));

622}

623

626}

627

632}

633

638}

639

643}

644

648}

649

651 return MCI.getOpcode() == Hexagon::A4_ext;

652}

653

658}

659

661 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);

662}

663

665 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||

666 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));

667}

668

669

674}

675

680}

681

682

684 MCInst const &MCI, unsigned short O) {

686}

687

692}

693

695 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||

696 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);

697}

698

700 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);

701}

702

704 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);

705}

706

707std::pair<unsigned, unsigned>

710 "VecRegPair must be a vector register pair");

711

713 const unsigned PairIndex =

714 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);

715

716 return IsRev ? std::make_pair(PairIndex, PairIndex + 1)

717 : std::make_pair(PairIndex + 1, PairIndex);

718}

719

724 ? Producer - Hexagon::WR0

725 : Producer - Hexagon::W0;

726 const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;

727

728 return ConsumerSingleIndex == ProdPairIndex;

729 }

730 return false;

731}

732

737}

738

741}

742

747}

748

749

754}

755

759 return (

761}

762

764 auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);

765 return PredRegClass.contains(Reg);

766}

767

769 MCInst const &Inst, unsigned I) {

771

773 Desc.operands()[I].RegClass == Hexagon::PredRegsRegClassID;

774}

775

776

780}

781

782

788}

789

795}

796

797

801}

802

807}

808

811 default:

812 return false;

813 case Hexagon::SA1_addi:

814 case Hexagon::SA1_addrx:

815 case Hexagon::SA1_addsp:

816 case Hexagon::SA1_and1:

817 case Hexagon::SA1_clrf:

818 case Hexagon::SA1_clrfnew:

819 case Hexagon::SA1_clrt:

820 case Hexagon::SA1_clrtnew:

821 case Hexagon::SA1_cmpeqi:

822 case Hexagon::SA1_combine0i:

823 case Hexagon::SA1_combine1i:

824 case Hexagon::SA1_combine2i:

825 case Hexagon::SA1_combine3i:

826 case Hexagon::SA1_combinerz:

827 case Hexagon::SA1_combinezr:

828 case Hexagon::SA1_dec:

829 case Hexagon::SA1_inc:

830 case Hexagon::SA1_seti:

831 case Hexagon::SA1_setin1:

832 case Hexagon::SA1_sxtb:

833 case Hexagon::SA1_sxth:

834 case Hexagon::SA1_tfr:

835 case Hexagon::SA1_zxtb:

836 case Hexagon::SA1_zxth:

837 case Hexagon::SL1_loadri_io:

838 case Hexagon::SL1_loadrub_io:

839 case Hexagon::SL2_deallocframe:

840 case Hexagon::SL2_jumpr31:

841 case Hexagon::SL2_jumpr31_f:

842 case Hexagon::SL2_jumpr31_fnew:

843 case Hexagon::SL2_jumpr31_t:

844 case Hexagon::SL2_jumpr31_tnew:

845 case Hexagon::SL2_loadrb_io:

846 case Hexagon::SL2_loadrd_sp:

847 case Hexagon::SL2_loadrh_io:

848 case Hexagon::SL2_loadri_sp:

849 case Hexagon::SL2_loadruh_io:

850 case Hexagon::SL2_return:

851 case Hexagon::SL2_return_f:

852 case Hexagon::SL2_return_fnew:

853 case Hexagon::SL2_return_t:

854 case Hexagon::SL2_return_tnew:

855 case Hexagon::SS1_storeb_io:

856 case Hexagon::SS1_storew_io:

857 case Hexagon::SS2_allocframe:

858 case Hexagon::SS2_storebi0:

859 case Hexagon::SS2_storebi1:

860 case Hexagon::SS2_stored_sp:

861 case Hexagon::SS2_storeh_io:

862 case Hexagon::SS2_storew_sp:

863 case Hexagon::SS2_storewi0:

864 case Hexagon::SS2_storewi1:

865 return true;

866 }

867}

868

872}

873

875 auto Sentinel = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())

876 << 8;

877 if (MCI.size() <= Index)

883 if (!MCO.getExpr()->evaluateAsAbsolute(Value))

886}

887

891}

892

894 HexagonMCExpr const &HExpr = cast(Expr);

896}

900}

902 HexagonMCExpr const &HExpr = cast(Expr);

904}

907 const_cast<HexagonMCExpr &>(*cast(&Expr));

909}

911 HexagonMCExpr const *HExpr = dyn_cast(&Expr);

912 if (!HExpr)

913 return false;

915}

916

918 const bool IsTiny = STI.hasFeature(Hexagon::ProcTinyCore);

919

921}

922

925 .Case("hexagonv67t", 3)

927}

928

935}

936

939 if (!isPredicated(MCII, MCI))

940 return {0, 0, false};

942 for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)

943 if (Desc.operands()[I].RegClass == Hexagon::PredRegsRegClassID)

945 return {0, 0, false};

946}

947

952}

953

956 default:

957 return false;

958 case Hexagon::V6_vgathermh:

959 case Hexagon::V6_vgathermhq:

960 case Hexagon::V6_vgathermhw:

961 case Hexagon::V6_vgathermhwq:

962 case Hexagon::V6_vgathermw:

963 case Hexagon::V6_vgathermwq:

964 return true;

965 }

966 return false;

967}

968

972}

973

976 const unsigned OpCode = MCI.getOpcode();

977 const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore];

978 const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||

979 (IsTiny && Hexagon::A2_nop == OpCode) ||

980 (IsTiny && Hexagon::J4_hintjumpr == OpCode);

981

982 return !NoSlotReqd;

983}

984

988 unsigned slotsUsed = 0;

990 MCInst const &MCI = *HMI.getInst();

992 continue;

994 slotsUsed += 2;

995 else

996 ++slotsUsed;

997 }

998 return slotsUsed;

999}

1000

1010 assert(Duplex != nullptr);

1013}

1014

1019}

1020

1026}

1027

1032}

1033

1037

1038

1041 return ((Consumer - Hexagon::V0) & 0x1) ^ Rev;

1042 }

1043 if (Producer2 != Hexagon::NoRegister)

1044 return Consumer == Producer;

1045 return 0;

1046}

1047

1049 return (

1054}

1055

1061 return (Desc.isBranch() || Desc.isCall() || Desc.isReturn());

1062}

unsigned const MachineRegisterInfo * MRI

#define HEXAGON_PACKET_OUTER_SIZE

#define HEXAGON_PACKET_INNER_SIZE

#define HEXAGON_PACKET_SIZE

#define HEXAGON_PRESHUFFLE_PACKET_SIZE

uint64_t IntrinsicInst * II

static bool isBranch(unsigned Opcode)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallVector class.

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

static SymbolRef::Type getType(const Symbol *Sym)

Check for a valid bundle.

void setMustNotExtend(bool Val=true)

bool mustNotExtend() const

void setMustExtend(bool Val=true)

void setS27_2_reloc(bool Val=true)

bool isPredicated() const

bool operator==(PacketIterator const &Other) const

PacketIterator & operator++()

MCInst const & operator*() const

PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)

static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

const MCRegisterInfo * getRegisterInfo() const

Base class for the full range of assembler expressions which are needed for parsing.

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

Describe properties that are true of each instruction in the target description file.

unsigned getSchedClass() const

Return the scheduling class for this instruction.

bool isPseudo() const

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

StringRef getName(unsigned Opcode) const

Returns the name for the instructions with the given opcode.

Instances of this class represent operands of the MCInst class.

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

void setInst(const MCInst *Val)

MCRegister getReg() const

Returns the register number.

const MCInst * getInst() const

const MCExpr * getExpr() const

static MCOperand createInst(const MCInst *Val)

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const FeatureBitset & getFeatureBits() const

const MCSchedModel & getSchedModel() const

Get the machine model for this subtarget's CPU.

Wrapper class representing virtual and physical registers.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

LLVM Value Representation.

A range adaptor for a pair of iterators.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned const TypeCVI_LAST

static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)

unsigned const TypeCVI_FIRST

@ RestrictNoSlot1StoreMask

@ RestrictNoSlot1StorePos

std::pair< unsigned, unsigned > GetVecRegPairIndices(MCRegister VecRegPair)

Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.

bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)

MCInst deriveSubInst(MCInst const &Inst)

bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)

bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn can be packaged only with an A-type insn in slot #1.

bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)

void setOuterLoop(MCInst &MCI)

bool isIntReg(MCRegister Reg)

void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)

unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)

bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn is solo, i.e., cannot be in a packet.

SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)

bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn is newly predicated.

bool IsReverseVecRegPair(MCRegister VecReg)

bool isOuterLoop(MCInst const &MCI)

MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)

unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)

size_t bundleSize(MCInst const &MCI)

bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)

bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)

Return the resources used by this instruction.

void padEndloop(MCInst &MCI, MCContext &Context)

constexpr int64_t memReorderDisabledMask

bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)

bool IsSingleConsumerRefPairProducer(MCRegister Producer, MCRegister Consumer)

bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)

void setS27_2_reloc(MCExpr const &Expr, bool Val=true)

unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)

Return the new value or the newly produced value.

bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn can be packaged only with A and X-type insns.

bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn expects newly produced value.

void setInnerLoop(MCInst &MCI)

unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)

bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)

bool isMemReorderDisabled(MCInst const &MCI)

unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)

bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)

bool IsVecRegPair(MCRegister VecReg)

bool mustNotExtend(MCExpr const &Expr)

bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)

Return true if the operand is a new-value store insn.

MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)

iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)

bool IsVecRegSingle(MCRegister VecReg)

bool LoopNeedsPadding(MCInst const &MCB)

void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)

tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...

void setMemReorderDisabled(MCInst &MCI)

bool isBundle(MCInst const &MCI)

int64_t minConstant(MCInst const &MCI, size_t Index)

bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)

bool isDblRegForSubInst(MCRegister Reg)

MCExpr const & getExpr(MCExpr const &Expr)

bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)

Return whether the operand is extendable.

int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)

Return the minimum value of an extendable operand.

bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)

bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)

bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)

bool isIntRegForSubInst(MCRegister Reg)

unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)

Return the slots used by the insn.

MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)

unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)

Return the Hexagon ISA class for the insn.

bool isImmext(MCInst const &MCI)

void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)

MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)

bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)

bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)

constexpr int64_t innerLoopMask

bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned SubregisterBit(MCRegister Consumer, MCRegister Producer, MCRegister Producer2)

constexpr size_t bundleInstructionsOffset

bool s27_2_reloc(MCExpr const &Expr)

bool hasImmExt(MCInst const &MCI)

bool isInnerLoop(MCInst const &MCI)

bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn produces a second value.

PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)

bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)

unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)

Return the slots this instruction consumes in addition to the slot(s) it can execute out of.

bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)

int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)

Return the maximum value of an extendable operand.

void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)

void setMustNotExtend(MCExpr const &Expr, bool Val=true)

bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)

unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)

void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)

bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)

StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)

unsigned packetSizeSlots(MCSubtargetInfo const &STI)

bool isPredReg(MCRegisterInfo const &MRI, MCRegister Reg)

bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)

bool hasExtenderForIndex(MCInst const &MCB, size_t Index)

bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)

constexpr int64_t outerLoopMask

MCInst const & instruction(MCInst const &MCB, size_t Index)

bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)

Return where the instruction is an accumulator.

bool mustExtend(MCExpr const &Expr)

bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)

MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)

bool isSubInstruction(MCInst const &MCI)

MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)

void setMustExtend(MCExpr const &Expr, bool Val=true)

unsigned getDuplexRegisterNumbering(MCRegister Reg)

bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)

bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)

bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether it is a floating-point insn.

bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)

Return whether the insn produces a value.

unsigned packetSize(StringRef CPU)

bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)

MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)

MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

cl::opt< bool > HexagonDisableCompound

bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

unsigned HexagonGetLastSlot()

const InstrStage HexagonStages[]

Description of the encoding of one expression Op.

An itinerary represents the scheduling information for an instruction.

const InstrItinerary * InstrItineraries