InstrEmitter.cpp Source File (original) (raw)

32using namespace llvm;

34#define DEBUG_TYPE "instr-emitter"

46 unsigned N = Node->getNumValues();

47 while (N && Node->getValueType(N - 1) == MVT::Glue)

48 --N;

49 if (N && Node->getValueType(N - 1) == MVT::Other)

50 --N;

51 return N;

52}

62 unsigned &NumImpUses) {

63 unsigned N = Node->getNumOperands();

64 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)

65 --N;

67 --N;

68 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)

69 --N;

72 NumImpUses = N - NumExpUses;

73 for (unsigned I = N; I > NumExpUses; --I) {

75 continue;

77 if (RN->getReg().isPhysical())

78 continue;

79 NumImpUses = N - I;

80 break;

81 }

83 return N;

84}

88void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,

89 VRBaseMapType &VRBaseMap) {

93 if (IsClone)

94 VRBaseMap.erase(Op);

95 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;

96 (void)isNew;

97 assert(isNew && "Node emitted out of order - early");

98 return;

99 }

100

101

102

103 bool MatchReg = true;

104 const TargetRegisterClass *UseRC = nullptr;

105 MVT VT = Op.getSimpleValueType();

106

107

108 if (TLI->isTypeLegal(VT))

109 UseRC = TLI->getRegClassFor(VT, Op->isDivergent());

110

111 for (SDNode *User : Op->users()) {

112 bool Match = true;

116 VRBase = DestReg;

117 Match = false;

118 } else if (DestReg != SrcReg)

119 Match = false;

120 } else {

121 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {

122 if (User->getOperand(i) != Op)

123 continue;

124 if (VT == MVT::Other || VT == MVT::Glue)

125 continue;

126 Match = false;

127 if (User->isMachineOpcode()) {

128 const MCInstrDesc &II = TII->get(User->getMachineOpcode());

129 const TargetRegisterClass *RC = nullptr;

130 if (i + II.getNumDefs() < II.getNumOperands()) {

131 RC = TRI->getAllocatableClass(

132 TII->getRegClass(II, i + II.getNumDefs()));

133 }

134 if (!UseRC)

135 UseRC = RC;

136 else if (RC) {

137 const TargetRegisterClass *ComRC =

138 TRI->getCommonSubClass(UseRC, RC);

139

140

141 if (ComRC)

142 UseRC = ComRC;

143 }

144 }

145 }

146 }

147 MatchReg &= Match;

148 if (VRBase)

149 break;

150 }

151

152 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;

153 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);

154

155

156 if (VRBase) {

157 DstRC = MRI->getRegClass(VRBase);

158 } else if (UseRC) {

159 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&

160 "Incompatible phys register def and uses!");

161 DstRC = UseRC;

162 } else

163 DstRC = SrcRC;

164

165

166

168 VRBase = SrcReg;

169 } else {

170

171 VRBase = MRI->createVirtualRegister(DstRC);

172 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), TII->get(TargetOpcode::COPY),

173 VRBase)

175 }

176

177 if (IsClone)

178 VRBaseMap.erase(Op);

179 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;

180 (void)isNew;

181 assert(isNew && "Node emitted out of order - early");

182}

183

184void InstrEmitter::CreateVirtualRegisters(SDNode *Node,

187 bool IsClone, bool IsCloned,

188 VRBaseMapType &VRBaseMap) {

189 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&

190 "IMPLICIT_DEF should have been handled as a special case elsewhere!");

191

193 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&

194 II.isVariadic() && II.variadicOpsAreDefs();

195 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();

196 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)

197 NumVRegs = NumResults;

198 for (unsigned i = 0; i < NumVRegs; ++i) {

199

200

201

203 const TargetRegisterClass *RC =

204 TRI->getAllocatableClass(TII->getRegClass(II, i));

205

206

207

208

209 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {

210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(

211 Node->getSimpleValueType(i),

212 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));

213 if (RC)

214 VTRC = TRI->getCommonSubClass(RC, VTRC);

215 if (VTRC)

216 RC = VTRC;

217 }

218

219 if (.operands().empty() && II.operands()[i].isOptionalDef()) {

220

224 }

225

226 if (!VRBase && !IsClone && !IsCloned)

227 for (SDNode *User : Node->users()) {

229 User->getOperand(2).getNode() == Node &&

230 User->getOperand(2).getResNo() == i) {

233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);

234 if (RegRC == RC) {

235 VRBase = Reg;

237 break;

238 }

239 }

240 }

241 }

242

243

244

245 if (!VRBase) {

246 assert(RC && "Isn't a register operand!");

247 VRBase = MRI->createVirtualRegister(RC);

249 }

250

251

252

253 if (i < NumResults) {

255 if (IsClone)

256 VRBaseMap.erase(Op);

257 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;

258 (void)isNew;

259 assert(isNew && "Node emitted out of order - early");

260 }

261 }

262}

263

264

265

266Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {

267 if (Op.isMachineOpcode() &&

268 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {

269

270

271

272 const TargetRegisterClass *RC = TLI->getRegClassFor(

273 Op.getSimpleValueType(), Op.getNode()->isDivergent());

274 Register VReg = MRI->createVirtualRegister(RC);

275 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),

276 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);

277 return VReg;

278 }

279

281 assert(I != VRBaseMap.end() && "Node emitted out of order - late");

282 return I->second;

283}

284

286 if (Op->isMachineOpcode()) {

287 switch (Op->getMachineOpcode()) {

288 case TargetOpcode::CONVERGENCECTRL_ANCHOR:

289 case TargetOpcode::CONVERGENCECTRL_ENTRY:

290 case TargetOpcode::CONVERGENCECTRL_LOOP:

291 case TargetOpcode::CONVERGENCECTRL_GLUE:

292 return true;

293 }

294 return false;

295 }

296

297

298

299

300 switch (Op->getOpcode()) {

301 case ISD::CONVERGENCECTRL_ANCHOR:

302 case ISD::CONVERGENCECTRL_ENTRY:

303 case ISD::CONVERGENCECTRL_LOOP:

304 case ISD::CONVERGENCECTRL_GLUE:

305 llvm_unreachable("Convergence control should have been selected by now.");

306 }

307 return false;

308}

309

310

311

312

313void

316 unsigned IIOpNum,

318 VRBaseMapType &VRBaseMap,

319 bool IsDebug, bool IsClone, bool IsCloned) {

320 assert(Op.getValueType() != MVT::Other &&

321 Op.getValueType() != MVT::Glue &&

322 "Chain and glue operands should occur at end of operand list!");

323

324 Register VReg = getVR(Op, VRBaseMap);

325

326 const MCInstrDesc &MCID = MIB->getDesc();

328 MCID.operands()[IIOpNum].isOptionalDef();

329

330

331

332

333

334 if (II) {

335 const TargetRegisterClass *OpRC = nullptr;

336 if (IIOpNum < II->getNumOperands())

337 OpRC = TII->getRegClass(*II, IIOpNum);

338

339 if (OpRC) {

341

342

343 if (Op.isMachineOpcode() &&

344 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)

345 MinNumRegs = 0;

346

347 const TargetRegisterClass *ConstrainedRC

348 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs);

349 if (!ConstrainedRC) {

350 OpRC = TRI->getAllocatableClass(OpRC);

351 assert(OpRC && "Constraints cannot be fulfilled for allocation");

352 Register NewVReg = MRI->createVirtualRegister(OpRC);

354 TII->get(TargetOpcode::COPY), NewVReg)

356 VReg = NewVReg;

357 } else {

359 "Constraining an allocatable VReg produced an unallocatable class?");

360 }

361 }

362 }

363

364

365

366

367

368

369

370

371

372

373

374

377 !(IsClone || IsCloned);

378 if (isKill) {

380 while (Idx > 0 &&

383 --Idx;

385 if (isTied)

386 isKill = false;

387 }

388

391}

392

393

394

395

398 VRBaseMapType &VRBaseMap, bool IsDebug,

399 bool IsClone, bool IsCloned) {

400 if (Op.isMachineOpcode()) {

401 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,

402 IsDebug, IsClone, IsCloned);

404 if (C->getAPIntValue().getSignificantBits() <= 64) {

405 MIB.addImm(C->getSExtValue());

406 } else {

408 ConstantInt::get(MF->getFunction().getContext(), C->getAPIntValue()));

409 }

411 MIB.addFPImm(F->getConstantFPValue());

414 MVT OpVT = Op.getSimpleValueType();

415 const TargetRegisterClass *IIRC =

416 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum)) : nullptr;

417 const TargetRegisterClass *OpRC =

418 TLI->isTypeLegal(OpVT)

419 ? TLI->getRegClassFor(OpVT,

420 Op.getNode()->isDivergent() ||

421 (IIRC && TRI->isDivergentRegClass(IIRC)))

422 : nullptr;

423

424 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {

425 Register NewVReg = MRI->createVirtualRegister(IIRC);

426 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),

427 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);

428 VReg = NewVReg;

429 }

430

431

432

433 bool Imp = II && (IIOpNum >= II->getNumOperands() && ->isVariadic());

439 TGA->getTargetFlags());

441 MIB.addMBB(BBNode->getBasicBlock());

447 int Offset = CP->getOffset();

448 Align Alignment = CP->getAlign();

449

450 unsigned Idx;

451 MachineConstantPool *MCP = MF->getConstantPool();

452 if (CP->isMachineConstantPoolEntry())

454 else

460 MIB.addSym(SymNode->getMCSymbol());

463 BA->getOffset(),

464 BA->getTargetFlags());

466 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());

467 } else {

468 assert(Op.getValueType() != MVT::Other &&

469 Op.getValueType() != MVT::Glue &&

470 "Chain and glue operands should occur at end of operand list!");

471 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,

472 IsDebug, IsClone, IsCloned);

473 }

474}

475

476Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,

478 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);

479 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);

480

481

482

483 if (RC && RC != VRC)

484 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);

485

486

487 if (RC)

488 return VReg;

489

490

491

492 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);

493 assert(RC && "No legal register class for VT supports that SubIdx");

494 Register NewReg = MRI->createVirtualRegister(RC);

495 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)

497 return NewReg;

498}

499

500

501

502void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,

503 bool IsClone, bool IsCloned) {

505 unsigned Opc = Node->getMachineOpcode();

506

507

508

509 for (SDNode *User : Node->users()) {

511 User->getOperand(2).getNode() == Node) {

514 VRBase = DestReg;

515 break;

516 }

517 }

518 }

519

520 if (Opc == TargetOpcode::EXTRACT_SUBREG) {

521

522

523

524 unsigned SubIdx = Node->getConstantOperandVal(1);

525 const TargetRegisterClass *TRC =

526 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());

527

529 MachineInstr *DefMI;

531 if (R && R->getReg().isPhysical()) {

532 Reg = R->getReg();

534 } else {

535 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);

536 DefMI = MRI->getVRegDef(Reg);

537 }

538

540 unsigned DefSubIdx;

542 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&

543 SubIdx == DefSubIdx &&

544 TRC == MRI->getRegClass(SrcReg)) {

545

546

547

548

549

550 VRBase = MRI->createVirtualRegister(TRC);

551 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),

552 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);

553 MRI->clearKillFlags(SrcReg);

554 } else {

555

556

557

559 Reg = ConstrainForSubReg(Reg, SubIdx,

560 Node->getOperand(0).getSimpleValueType(),

561 Node->isDivergent(), Node->getDebugLoc());

562

563 if (!VRBase)

564 VRBase = MRI->createVirtualRegister(TRC);

565

566

567 MachineInstrBuilder CopyMI =

568 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),

569 TII->get(TargetOpcode::COPY), VRBase);

572 else

573 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));

574 }

575 } else if (Opc == TargetOpcode::INSERT_SUBREG ||

576 Opc == TargetOpcode::SUBREG_TO_REG) {

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596 const TargetRegisterClass *SRC =

597 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());

598 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);

599 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");

600

601 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))

602 VRBase = MRI->createVirtualRegister(SRC);

603

604

605 MachineInstrBuilder MIB =

606 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);

607

608

609

610 if (Opc == TargetOpcode::SUBREG_TO_REG) {

613 } else

614 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, false,

615 IsClone, IsCloned);

616

617 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, false,

618 IsClone, IsCloned);

620 MBB->insert(InsertPos, MIB);

621 } else

622 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");

623

625 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;

626 (void)isNew;

627 assert(isNew && "Node emitted out of order - early");

628}

629

630

631

632

633

634void

635InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,

636 VRBaseMapType &VRBaseMap) {

637

638 unsigned DstRCIdx = Node->getConstantOperandVal(1);

639 const TargetRegisterClass *DstRC =

640 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));

641 Register NewVReg = MRI->createVirtualRegister(DstRC);

642 const MCInstrDesc &II = TII->get(TargetOpcode::COPY);

643 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);

644 AddOperand(MIB, Node->getOperand(0), 1, &II, VRBaseMap, false,

645 false, false);

646

647 MBB->insert(InsertPos, MIB);

649 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;

650 (void)isNew;

651 assert(isNew && "Node emitted out of order - early");

652}

653

654

655

656void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,

657 bool IsClone, bool IsCloned) {

658 unsigned DstRCIdx = Node->getConstantOperandVal(0);

659 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);

660 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));

661 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);

662 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);

663 unsigned NumOps = Node->getNumOperands();

664

665

666

667 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)

668 --NumOps;

669

671 "REG_SEQUENCE must have an odd number of operands!");

672 for (unsigned i = 1; i != NumOps; ++i) {

674 if ((i & 1) == 0) {

676

677

678 if (!R || ->getReg().isPhysical()) {

679 unsigned SubIdx = Op->getAsZExtVal();

681 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);

682 const TargetRegisterClass *SRC =

683 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);

684 if (SRC && SRC != RC) {

685 MRI->setRegClass(NewVReg, SRC);

686 RC = SRC;

687 }

688 }

689 }

690 AddOperand(MIB, Op, i+1, &II, VRBaseMap, false,

691 IsClone, IsCloned);

692 }

693

694 MBB->insert(InsertPos, MIB);

696 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;

697 (void)isNew;

698 assert(isNew && "Node emitted out of order - early");

699}

700

701

702

708 ->isValidLocationForIntrinsic(DL) &&

709 "Expected inlined-at fields to agree");

710

712

714 "dbg_value with no location operands?");

715

718

719

720 if (EmitDebugInstrRefs)

722 return InstrRef;

723

724

725

728

729

730

732}

733

735 const Value *V = Op.getConst();

737 if (CI->getBitWidth() > 64)

739 if (CI->getBitWidth() == 1)

742 }

745

748

750 0U, false, false,

751 false, false,

752 false, false,

753 0, true);

754}

755

761 switch (Op.getKind()) {

764 break;

767 break;

770

771

772

773

774

775 if (VRBaseMap.count(V) == 0)

776 MIB.addReg(0U);

777 else

778 AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,

779 true, false, false);

780 } break;

783 break;

784 }

785 }

786}

787

794 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);

795

796

797

800 };

801

802

805 };

806

807

808

814 }

815

816

817

820

821

824

826

827

828

829

830

831

832

833

834

835

836 auto AddVRegOp = [&](Register VReg) {

838 VReg, false, false,

839 false, false,

840 false, false,

841 0, true));

842 };

846

847

850

852 VReg = DbgOperand.getVReg();

853

854

855

856 if (!MRI->hasOneDef(VReg)) {

857 AddVRegOp(VReg);

858 continue;

859 }

860

861 DefMI = &*MRI->def_instr_begin(VReg);

863

867

868 if (I == VRBaseMap.end())

869 break;

870

871

872 VReg = getVR(Op, VRBaseMap);

873

874

875

876 if (!MRI->hasOneDef(VReg)) {

877 AddVRegOp(VReg);

878 continue;

879 }

880

881 DefMI = &*MRI->def_instr_begin(VReg);

882 } else {

885 continue;

886 }

887

888

889

890

891 if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI)) {

892 AddVRegOp(VReg);

893 continue;

894 }

895

896

897 unsigned OperandIdx = 0;

898 for (const auto &MO : DefMI->operands()) {

899 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)

900 break;

901 ++OperandIdx;

902 }

903 assert(OperandIdx < DefMI->getNumOperands());

904

905

906 unsigned InstrNum = DefMI->getDebugInstrNum();

908 }

909

910

911

912 if (MOs.size() != OpCount)

914

915 return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);

916}

917

929

936

937 const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);

938

939 auto MIB = BuildMI(*MF, DL, DbgValDesc);

943 return &*MIB;

944}

945

952 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);

953

955 "Non variadic dbg_value should have only one location op");

956

957

958

961 const Value *V = LocationOps[0].getConst();

965 }

966 }

967

968

969

972

975 else

977

979}

980

986 "Expected inlined-at fields to agree");

987

988 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);

991

992 return &*MIB;

993}

994

995

996

997

998void InstrEmitter::

999EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,

1000 VRBaseMapType &VRBaseMap) {

1001 unsigned Opc = Node->getMachineOpcode();

1002

1003

1004 if (Opc == TargetOpcode::EXTRACT_SUBREG ||

1005 Opc == TargetOpcode::INSERT_SUBREG ||

1006 Opc == TargetOpcode::SUBREG_TO_REG) {

1007 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);

1008 return;

1009 }

1010

1011

1012 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {

1013 EmitCopyToRegClassNode(Node, VRBaseMap);

1014 return;

1015 }

1016

1017

1018 if (Opc == TargetOpcode::REG_SEQUENCE) {

1019 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);

1020 return;

1021 }

1022

1023 if (Opc == TargetOpcode::IMPLICIT_DEF)

1024

1025 return;

1026

1027 const MCInstrDesc &II = TII->get(Opc);

1029 unsigned NumDefs = II.getNumDefs();

1030 const MCPhysReg *ScratchRegs = nullptr;

1031

1032

1033 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {

1034

1035

1036

1038 if (Opc == TargetOpcode::PATCHPOINT) {

1040 NumDefs = NumResults;

1041 }

1042 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);

1043 } else if (Opc == TargetOpcode::STATEPOINT) {

1044 NumDefs = NumResults;

1045 }

1046

1047 unsigned NumImpUses = 0;

1048 unsigned NodeOperands =

1049 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);

1050 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&

1051 II.isVariadic() && II.variadicOpsAreDefs();

1052 bool HasPhysRegOuts = NumResults > NumDefs && .implicit_defs().empty() &&

1053 !HasVRegVariadicDefs;

1054#ifndef NDEBUG

1055 unsigned NumMIOperands = NodeOperands + NumResults;

1056 if (II.isVariadic())

1057 assert(NumMIOperands >= II.getNumOperands() &&

1058 "Too few operands for a variadic node!");

1059 else

1060 assert(NumMIOperands >= II.getNumOperands() &&

1061 NumMIOperands <=

1062 II.getNumOperands() + II.implicit_defs().size() + NumImpUses &&

1063 "#operands for dag node doesn't match .td file!");

1064#endif

1065

1066

1067 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);

1068

1069

1071 const SDNodeFlags Flags = Node->getFlags();

1072 if (Flags.hasUnpredictable())

1074

1075

1076

1077 if (NumResults) {

1078 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);

1079

1080 if (Flags.hasNoSignedZeros())

1082

1083 if (Flags.hasAllowReciprocal())

1085

1086 if (Flags.hasNoNaNs())

1088

1089 if (Flags.hasNoInfs())

1091

1092 if (Flags.hasAllowContract())

1094

1095 if (Flags.hasApproximateFuncs())

1097

1098 if (Flags.hasAllowReassociation())

1100

1101 if (Flags.hasNoUnsignedWrap())

1103

1104 if (Flags.hasNoSignedWrap())

1106

1107 if (Flags.hasExact())

1109

1110 if (Flags.hasNoFPExcept())

1112

1113 if (Flags.hasDisjoint())

1115

1116 if (Flags.hasSameSign())

1118 }

1119

1120

1121

1122 bool HasOptPRefs = NumDefs > NumResults;

1123 assert((!HasOptPRefs || !HasPhysRegOuts) &&

1124 "Unable to cope with optional defs and phys regs defs!");

1125 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;

1126 for (unsigned i = NumSkip; i != NodeOperands; ++i)

1127 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,

1128 VRBaseMap, false, IsClone, IsCloned);

1129

1130

1131 if (ScratchRegs)

1132 for (unsigned i = 0; ScratchRegs[i]; ++i)

1135

1136

1137

1139

1140

1142

1143

1144

1145

1146 MBB->insert(InsertPos, MIB);

1147

1148

1149

1150

1151

1152

1153

1154

1155

1156

1157

1158

1159

1160

1161

1162

1164

1165

1166 if (HasPhysRegOuts) {

1167 for (unsigned i = NumDefs; i < NumResults; ++i) {

1169 if ( Node ->hasAnyUseOfValue(i))

1170 continue;

1171

1173 EmitCopyFromReg(SDValue(Node, i), IsClone, Reg, VRBaseMap);

1174 }

1175 }

1176

1177

1178 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {

1179 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {

1184 continue;

1186

1187 continue;

1188 }

1189

1190 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());

1192

1193

1194 for (const SDValue &Op : F->op_values())

1199 }

1200 }

1201 }

1202

1203

1204 if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {

1207 }

1208

1209

1210 if (!UsedRegs.empty() || .implicit_defs().empty() || II.hasOptionalDef())

1212

1213

1214

1215 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {

1216 assert(!HasPhysRegOuts && "STATEPOINT mishandled");

1217 MachineInstr *MI = MIB;

1218 unsigned Def = 0;

1219 int First = StatepointOpers(MI).getFirstGCPtrIdx();

1220 assert(First > 0 && "Statepoint has Defs but no GC ptr list");

1221 unsigned Use = (unsigned)First;

1222 while (Def < NumDefs) {

1223 if (MI->getOperand(Use).isReg())

1224 MI->tieOperands(Def++, Use);

1226 }

1227 }

1228

1229 unsigned Op = Node->getNumOperands();

1230 if (Op != 0 && Node->getOperand(Op - 1)->getOpcode() ==

1231 ~(unsigned)TargetOpcode::CONVERGENCECTRL_GLUE) {

1232 Register VReg = getVR(Node->getOperand(Op - 1)->getOperand(0), VRBaseMap);

1234 true);

1236 Op--;

1237 }

1238

1239 if (Op != 0 &&

1241 MI->setDeactivationSymbol(

1242 *MF, const_cast<GlobalValue *>(

1244 ->getGlobal()));

1245 Op--;

1246 }

1247

1248

1249 if (II.hasPostISelHook())

1250 TLI->AdjustInstrPostInstrSelection(*MIB, Node);

1251}

1252

1253

1254

1255void InstrEmitter::

1256EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,

1257 VRBaseMapType &VRBaseMap) {

1258 switch (Node->getOpcode()) {

1259 default:

1260#ifndef NDEBUG

1261 Node->dump();

1262#endif

1263 llvm_unreachable("This target-independent node should have been selected!");

1268 break;

1274

1275

1276 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),

1277 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);

1278 break;

1279 }

1282 SrcReg = R->getReg();

1283 else

1284 SrcReg = getVR(SrcVal, VRBaseMap);

1285

1286 if (SrcReg == DestReg)

1287 break;

1288

1289 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),

1290 DestReg).addReg(SrcReg);

1291 break;

1292 }

1295 EmitCopyFromReg(SDValue(Node, 0), IsClone, SrcReg, VRBaseMap);

1296 break;

1297 }

1298 case ISD::EH_LABEL:

1299 case ISD::ANNOTATION_LABEL: {

1300 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)

1301 ? TargetOpcode::EH_LABEL

1302 : TargetOpcode::ANNOTATION_LABEL;

1304 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),

1306 break;

1307 }

1308

1309 case ISD::LIFETIME_START:

1310 case ISD::LIFETIME_END: {

1311 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)

1312 ? TargetOpcode::LIFETIME_START

1313 : TargetOpcode::LIFETIME_END;

1315 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))

1317 break;

1318 }

1319

1320 case ISD::PSEUDO_PROBE: {

1321 unsigned TarOp = TargetOpcode::PSEUDO_PROBE;

1325

1326 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))

1331 break;

1332 }

1333

1334 case ISD::INLINEASM:

1335 case ISD::INLINEASM_BR: {

1336 unsigned NumOps = Node->getNumOperands();

1337 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)

1338 --NumOps;

1339

1340

1341 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR

1342 ? TargetOpcode::INLINEASM_BR

1343 : TargetOpcode::INLINEASM;

1344 MachineInstrBuilder MIB =

1345 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));

1346

1347

1351

1352

1353

1354 int64_t ExtraInfo =

1356 getZExtValue();

1357 MIB.addImm(ExtraInfo);

1358

1359

1360 SmallVector<unsigned, 8> GroupIdx;

1361

1362

1364

1365

1367 unsigned Flags = Node->getConstantOperandVal(i);

1368 const InlineAsm::Flag F(Flags);

1369 const unsigned NumVals = F.getNumOperandRegisters();

1370

1373 ++i;

1374

1375 switch (F.getKind()) {

1377 for (unsigned j = 0; j != NumVals; ++j, ++i) {

1379

1380

1381

1383 }

1384 break;

1387 for (unsigned j = 0; j != NumVals; ++j, ++i) {

1392 }

1393 break;

1397

1398

1399 for (unsigned j = 0; j != NumVals; ++j, ++i)

1400 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,

1401 false, IsClone, IsCloned);

1402

1403

1404 if (F.isRegUseKind()) {

1405 unsigned DefGroup;

1406 if (F.isUseOperandTiedToDef(DefGroup)) {

1407 unsigned DefIdx = GroupIdx[DefGroup] + 1;

1408 unsigned UseIdx = GroupIdx.back() + 1;

1409 for (unsigned j = 0; j != NumVals; ++j)

1410 MIB->tieOperands(DefIdx + j, UseIdx + j);

1411 }

1412 }

1413 break;

1415 for (unsigned j = 0; j != NumVals; ++j, ++i) {

1417 AddOperand(MIB, Op, 0, nullptr, VRBaseMap,

1418 false, IsClone, IsCloned);

1419

1420

1422 unsigned NewFlags =

1423 MF->getSubtarget().classifyGlobalFunctionReference(

1424 TGA->getGlobal());

1427 }

1428 }

1429 }

1430 }

1431

1432

1433

1434

1435

1436

1439 MachineOperand *MO =

1441 assert(MO && "No def operand for clobbered register?");

1443 }

1444 }

1445

1446

1449 if (MD)

1451

1452

1453 if (MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {

1457 }

1458

1459 MBB->insert(InsertPos, MIB);

1460 break;

1461 }

1462 }

1463}

1464

1465

1466

1469 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),

1470 TII(MF->getSubtarget().getInstrInfo()),

1471 TRI(MF->getSubtarget().getRegisterInfo()),

1472 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),

1473 InsertPos(insertpos) {

1474 EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();

1475}

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static const Function * getParent(const Value *V)

This file contains constants used for implementing Dwarf debug support.

static bool isConvergenceCtrlMachineOp(SDValue Op)

Definition InstrEmitter.cpp:285

MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op)

Definition InstrEmitter.cpp:734

const unsigned MinRCSize

MinRCSize - Smallest register class we allow when constraining virtual registers.

Definition InstrEmitter.cpp:40

static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)

countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...

Definition InstrEmitter.cpp:61

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...

Promote Memory to Register

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

This file describes how to lower LLVM code to machine code.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

ConstantFP - Floating Point Values [float, double].

This is the shared class of boolean and integer constants.

uint64_t getZExtValue() const

static LLVM_ABI DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)

Append the opcodes Ops to DIExpr.

LLVM_ABI std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)

Try to shorten an expression with an initial constant operand.

static LLVM_ABI const DIExpression * convertToVariadicExpression(const DIExpression *Expr)

If Expr is a non-variadic expression (i.e.

static LLVM_ABI const DIExpression * convertToUndefExpression(const DIExpression *Expr)

Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...

Base class for variables.

iterator find(const_arg_type_t< KeyT > Val)

DenseMapIterator< KeyT, ValueT, KeyInfoT, BucketT > iterator

size_type count(const_arg_type_t< KeyT > Val) const

Return 1 if the specified key is in the map, 0 otherwise.

MachineInstr * EmitDbgValue(SDDbgValue *SD, VRBaseMapType &VRBaseMap)

EmitDbgValue - Generate machine instruction for a dbg_value node.

Definition InstrEmitter.cpp:704

MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, VRBaseMapType &VRBaseMap)

Emit a dbg_value as a DBG_INSTR_REF.

Definition InstrEmitter.cpp:789

SmallDenseMap< SDValue, Register, 16 > VRBaseMapType

MachineInstr * EmitDbgLabel(SDDbgLabel *SD)

Generate machine instruction for a dbg_label node.

Definition InstrEmitter.cpp:982

MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)

Emit a DBG_VALUE $noreg, indicating a variable has no location.

Definition InstrEmitter.cpp:918

static unsigned CountResults(SDNode *Node)

CountResults - The results of target nodes have register or immediate operands first,...

Definition InstrEmitter.cpp:45

MachineInstr * EmitDbgValueList(SDDbgValue *SD, VRBaseMapType &VRBaseMap)

Emit a DBG_VALUE_LIST from the operands to SDDbgValue.

Definition InstrEmitter.cpp:931

InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)

InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...

Definition InstrEmitter.cpp:1467

void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, VRBaseMapType &VRBaseMap)

Definition InstrEmitter.cpp:756

MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, VRBaseMapType &VRBaseMap)

Emit a DBG_VALUE from the operands to SDDbgValue.

Definition InstrEmitter.cpp:947

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

ArrayRef< MCOperandInfo > operands() const

int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const

Returns the value of the specified operand constraint if it is present.

ArrayRef< MCPhysReg > implicit_uses() const

Return a list of registers that are potentially read by any instance of this machine instruction.

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

MachineInstrBundleIterator< MachineInstr > iterator

unsigned getConstantPoolIndex(const Constant *C, Align Alignment)

getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.

const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const

const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const

const MachineInstrBuilder & addCImm(const ConstantInt *Val) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addMetadata(const MDNode *MD) const

const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const

const MachineInstrBuilder & addFrameIndex(int Idx) const

const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const

const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const

const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Representation of each machine instruction.

LLVM_ABI void setCFIType(MachineFunction &MF, uint32_t Type)

Set the CFI type for the instruction.

bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const

Return true if the MachineInstr reads the specified register.

unsigned getNumOperands() const

Retuns the total number of operands.

LLVM_ABI void addOperand(MachineFunction &MF, const MachineOperand &Op)

Add the specified operand to the instruction.

const MCInstrDesc & getDesc() const

Returns the target instruction descriptor of this MachineInstr.

LLVM_ABI void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)

Inserts Ops BEFORE It. Can untie/retie tied operands.

LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

LLVM_ABI void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

const MachineOperand & getOperand(unsigned i) const

MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...

MachineOperand class - Representation of each machine instruction operand.

static MachineOperand CreateFPImm(const ConstantFP *CFP)

bool isReg() const

isReg - Tests if this is a MO_Register operand.

static MachineOperand CreateCImm(const ConstantInt *CI)

void setIsEarlyClobber(bool Val=true)

static MachineOperand CreateImm(int64_t Val)

static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)

void setTargetFlags(unsigned F)

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Holds the information from a dbg_label node through SDISel.

MDNode * getLabel() const

Returns the MDNode pointer for the label.

const DebugLoc & getDebugLoc() const

Returns the DebugLoc.

Holds the information for a single machine location through SDISel; either an SDNode,...

Returns the Virtual Register for a VReg.

unsigned getResNo() const

Returns the ResNo for a register ref.

static SDDbgOperand fromConst(const Value *Const)

SDNode * getSDNode() const

Returns the SDNode* for a register ref.

@ VREG

Value is a virtual register.

@ FRAMEIX

Value is contents of a stack location.

@ SDNODE

Value is the result of an expression.

@ CONST

Value is a constant.

Holds the information from a dbg_value node through SDISel.

const DebugLoc & getDebugLoc() const

Returns the DebugLoc.

DIVariable * getVariable() const

Returns the DIVariable pointer for the variable.

bool isInvalidated() const

ArrayRef< SDDbgOperand > getLocationOps() const

DIExpression * getExpression() const

Returns the DIExpression pointer for the expression.

bool isIndirect() const

Returns whether this is an indirect value.

void setIsEmitted()

setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...

Represents one node in the SelectionDAG.

uint64_t getAsZExtVal() const

Helper method returns the zero-extended integer value of a ConstantSDNode.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

bool isMachineOpcode() const

unsigned getMachineOpcode() const

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

static LLVM_ABI unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)

Get index of next meta operand.

Primary interface to the complete machine description for the target machine.

bool isAllocatable() const

Return true if this register class may be used to create virtual registers.

bool hasSubClassEq(const TargetRegisterClass *RC) const

Returns true if RC is a sub-class of or equal to this class.

bool expensiveOrImpossibleToCopy() const

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ AnyReg

OBSOLETED - Used for stack based JavaScript calls.

@ C

The default llvm calling convention, compatible with C.

@ MERGE_VALUES

MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...

@ CopyFromReg

CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...

@ EntryToken

EntryToken - This is the marker used to indicate the start of a region.

@ CopyToReg

CopyToReg - This node has three operands: a chain, a register number to set to this value,...

@ TokenFactor

TokenFactor - This node takes multiple tokens as input and produces a single token result.

@ Define

@ EarlyClobber

@ User

could "use" a pointer

NodeAddr< DefNode * > Def

NodeAddr< UseNode * > Use

NodeAddr< NodeBase * > Node

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

void append_range(Container &C, Range &&R)

Wrapper function to append range R to container C.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

unsigned getImplRegState(bool B)

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

unsigned getDebugRegState(bool B)

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

unsigned getDefRegState(bool B)

unsigned getKillRegState(bool B)

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

TODO: Might pack better if we changed this to a Struct of Arrays, since MachineOperand is width 32,...