M68kInstrInfo.cpp Source File (original) (raw)

33#include

35using namespace llvm;

37#define DEBUG_TYPE "M68k-instr-info"

39#define GET_INSTRINFO_CTOR_DTOR

40#include "M68kGenInstrInfo.inc"

43void M68kInstrInfo::anchor() {}

51 switch (BrOpc) {

52 default:

54 case M68k::Beq8:

56 case M68k::Bne8:

58 case M68k::Blt8:

60 case M68k::Ble8:

62 case M68k::Bgt8:

64 case M68k::Bge8:

66 case M68k::Bcs8:

68 case M68k::Bls8:

70 case M68k::Bhi8:

72 case M68k::Bcc8:

74 case M68k::Bmi8:

76 case M68k::Bpl8:

78 case M68k::Bvs8:

80 case M68k::Bvc8:

82 }

83}

89 bool AllowModify) const {

91 auto UncondBranch =

92 std::pair<MachineBasicBlock::reverse_iterator, MachineBasicBlock *>{

93 MBB.rend(), nullptr};

96 std::vector<std::reference_wrapperllvm::MachineInstr> EraseList;

98 for (auto &Ref : EraseList)

99 Ref.get().eraseFromParent();

100 });

101

102

103

104 for (auto iter = MBB.rbegin(); iter != MBB.rend(); iter = std::next(iter)) {

105

106 unsigned Opcode = iter->getOpcode();

107

108 if (iter->isDebugInstr())

109 continue;

110

111

112

113 if (!isUnpredicatedTerminator(*iter))

114 break;

115

116

117

118 if (!iter->isBranch())

119 return true;

120

121

122 if (Opcode == M68k::BRA8 || Opcode == M68k::BRA16) {

123 if (!iter->getOperand(0).isMBB())

124 return true;

125 UncondBranch = {iter, iter->getOperand(0).getMBB()};

126

127

128 TBB = UncondBranch.second;

129

130 if (!AllowModify)

131 continue;

132

133

134 EraseList.insert(EraseList.begin(), MBB.rbegin(), iter);

135

136 Cond.clear();

137 FBB = nullptr;

138

139

140 if (MBB.isLayoutSuccessor(UncondBranch.second)) {

141 TBB = nullptr;

142 EraseList.push_back(*iter);

143 UncondBranch = {MBB.rend(), nullptr};

144 }

145

146 continue;

147 }

148

149

151

152

154 return true;

155

156

157

158

159

160

161

162

163 if (Cond.empty()) {

164 if (!iter->getOperand(0).isMBB())

165 return true;

166 MachineBasicBlock *CondBranchTarget = iter->getOperand(0).getMBB();

167

168

169

170

171

172

173

174

175

176 if (UncondBranch.first != MBB.rend()) {

177

178 assert(std::next(UncondBranch.first) == iter && "Wrong block layout.");

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197 if (AllowModify && MBB.isLayoutSuccessor(CondBranchTarget)) {

198

201

202 BuildMI(MBB, *UncondBranch.first, MBB.rfindDebugLoc(iter), get(BNCC))

203 .addMBB(UncondBranch.second);

204

205 EraseList.push_back(*iter);

206 EraseList.push_back(*UncondBranch.first);

207

208 TBB = UncondBranch.second;

209 FBB = nullptr;

211

212

213 } else {

214 TBB = CondBranchTarget;

215 FBB = UncondBranch.second;

217 }

218

219 UncondBranch = {MBB.rend(), nullptr};

220 continue;

221 }

222

223 TBB = CondBranchTarget;

224 FBB = nullptr;

226

227 continue;

228 }

229

230

231

232

235

236

238 if (!iter->getOperand(0).isMBB())

239 return true;

240 auto NewTBB = iter->getOperand(0).getMBB();

241 if (OldBranchCode == BranchCode && TBB == NewTBB)

242 continue;

243

244

245 return true;

246 }

247

248 return false;

249}

250

255 bool AllowModify) const {

257}

258

260 int *BytesRemoved) const {

261 assert(!BytesRemoved && "code size not handled");

262

264 unsigned Count = 0;

265

266 while (I != MBB.begin()) {

267 --I;

268 if (I->isDebugValue())

269 continue;

270 if (I->getOpcode() != M68k::BRA8 &&

272 break;

273

274 I->eraseFromParent();

275 I = MBB.end();

277 }

278

280}

281

285

286 assert(TBB && "InsertBranch must not be told to insert a fallthrough");

288 "M68k branch conditions have one component!");

289 assert(!BytesAdded && "code size not handled");

290

291 if (Cond.empty()) {

292

293 assert(!FBB && "Unconditional branch with multiple successors!");

295 return 1;

296 }

297

298

299 bool FallThru = FBB == nullptr;

300

301

302 unsigned Count = 0;

307 if (!FallThru) {

308

311 }

313}

314

317 unsigned Reg, MVT From, MVT To) const {

318 if (From == MVT::i8) {

319 unsigned R = Reg;

320

321 if (To == MVT::i32) {

322 R = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);

323 assert(R && "No viable SUB register available");

324 }

326 }

327

328 if (To == MVT::i32)

330}

331

334 unsigned Reg, MVT From, MVT To) const {

335

336 unsigned Mask, And;

337 if (From == MVT::i8)

338 Mask = 0xFF;

339 else

340 Mask = 0xFFFF;

341

342 if (To == MVT::i16)

343 And = M68k::AND16di;

344 else

345 And = M68k::AND32di;

346

347

349}

350

351

352

356 bool IsAddressReg = false;

357

358 const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID);

359 const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID);

360 const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID);

361

362 if (AR16->contains(Reg) || AR32->contains(Reg))

363 IsAddressReg = true;

364

365

367 MVTSize == MVT::i32

368 ? Reg

369 : Register(RI.getMatchingMegaReg(Reg, IsAddressReg ? AR32 : DR32));

370 assert(SReg && "No viable MEGA register available");

371

373

374

375 if (MVTSize == MVT::i8 || (!IsAddressReg && Imm >= -128 && Imm <= 127)) {

377

380

381

382

383 } else if (DR32->contains(Reg) && isUInt<8>(Imm)) {

385

388

389 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex8Lo);

390 assert(SubReg && "No viable SUB register available");

391

394

396

397

398 } else if (IsAddressReg && Imm == 0) {

400

403

407

409

410

411

412

413

414

415 } else if (AR32->contains(Reg) && isUInt<16>(Imm)) {

417

418 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);

419 assert(SubReg && "No viable SUB register available");

420

423

424

425 } else {

427 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri));

428 }

429

430 return true;

431}

432

434 MVT MVTSrc) const {

435 unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;

438

439 assert(Dst != Src && "You cannot use the same Regs with MOVX_RR");

440

442

443 const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);

444 const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);

445

446 assert(RCDst && RCSrc && "Wrong use of MOVX_RR");

447 assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVX_RR");

448 (void)RCSrc;

449

450

451 unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);

452 assert(SSrc && "No viable MEGA register available");

453

455

456

457

458 if (Dst == SSrc) {

461 } else {

465 }

466

467 return true;

468}

469

470

471

473 MVT MVTDst, MVT MVTSrc) const {

475

476 unsigned Move;

477

478 if (MVTDst == MVT::i16)

479 Move = M68k::MOV16rr;

480 else

481 Move = M68k::MOV32rr;

482

485

486 assert(Dst != Src && "You cannot use the same Regs with MOVSX_RR");

487

489

490 const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);

491 const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);

492

493 assert(RCDst && RCSrc && "Wrong use of MOVSX_RR");

494 assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVSX_RR");

495 (void)RCSrc;

496

497

498 unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);

499 assert(SSrc && "No viable MEGA register available");

500

503

504 if (Dst != SSrc) {

507 }

508

509 if (IsSigned) {

512 } else {

515 }

516

518

519 return true;

520}

521

524 MVT MVTSrc) const {

526

528

529

530

531

532

533

534 unsigned SubDst =

535 RI.getSubReg(Dst, MVTSrc == MVT::i8 ? M68k::MxSubRegIndex8Lo

536 : M68k::MxSubRegIndex16Lo);

537 assert(SubDst && "No viable SUB register available");

538

539

542

544 I++;

547

548 if (IsSigned) {

551 } else {

554 }

555

556 return true;

557}

558

562 I++;

566 if (IsPush)

568 else

570

572 return true;

573}

574

581

582 if (IsRM) {

586 } else {

590 }

591

592 unsigned Mask = 1 << RI.getSpillRegisterOrder(Reg);

593 if (IsRM) {

600 } else {

607 }

608

610

611 return true;

612}

613

614

615

616

617

618

619

620

623 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");

626

627

628

630

633 return true;

634}

635

638 switch (MI.getOpcode()) {

639 case M68k::PUSH8d:

641 case M68k::PUSH16d:

643 case M68k::PUSH32r:

645

646 case M68k::POP8d:

648 case M68k::POP16d:

650 case M68k::POP32r:

652

653 case M68k::SETCS_C8d:

655 case M68k::SETCS_C16d:

657 case M68k::SETCS_C32d:

659 }

660 return false;

661}

662

666

667

668

669

671 const unsigned NameIndices = M68kInstrNameIndices[MI->getOpcode()];

672 StringRef InstrName(&M68kInstrNameData[NameIndices]);

673 const unsigned OperandNo = MO.getOperandNo();

674

675

676

677 if (OperandNo == 1)

678 return Regex("[A-Z]+(8|16|32)k[a-z](_TC)?$").match(InstrName);

679

680

681

682 if (OperandNo == MI->getNumExplicitOperands() - 1)

683 return Regex("[A-Z]+(8|16|32)[a-z]k(_TC)?$").match(InstrName);

684

685 return false;

686}

687

691 Register SrcReg, bool KillSrc,

692 bool RenamableDest, bool RenamableSrc) const {

694 unsigned Opc = 0;

695

696

697 if (M68k::XR32RegClass.contains(DstReg, SrcReg))

698 Opc = M68k::MOV32rr;

699 else if (M68k::XR16RegClass.contains(DstReg, SrcReg))

700 Opc = M68k::MOV16rr;

701 else if (M68k::DR8RegClass.contains(DstReg, SrcReg))

702 Opc = M68k::MOV8dd;

703

704 if (Opc) {

707 return;

708 }

709

710

711

712

713

714

715

717 if (M68k::DR8RegClass.contains(SrcReg)) {

718 if (M68k::XR16RegClass.contains(DstReg))

719 Opc = M68k::MOVXd16d8;

720 else if (M68k::XR32RegClass.contains(DstReg))

721 Opc = M68k::MOVXd32d8;

722 } else if (M68k::XR16RegClass.contains(SrcReg) &&

723 M68k::XR32RegClass.contains(DstReg))

724 Opc = M68k::MOVXd32d16;

725

726 if (Opc) {

729 return;

730 }

731

732 bool FromCCR = SrcReg == M68k::CCR;

733 bool FromSR = SrcReg == M68k::SR;

734 bool ToCCR = DstReg == M68k::CCR;

735 bool ToSR = DstReg == M68k::SR;

736

737 if (FromCCR) {

738 Opc = M68k::MOV16dc;

739 if ( Subtarget .atLeastM68010()) {

740 Opc = M68k::MOV16ds;

741 SrcReg = M68k::SR;

742 }

743 if (!M68k::DR8RegClass.contains(DstReg) &&

744 !M68k::DR16RegClass.contains(DstReg) &&

745 !M68k::DR32RegClass.contains(DstReg)) {

746 LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');

748 }

749 } else if (ToCCR) {

750 Opc = M68k::MOV16cd;

751 if (M68k::DR8RegClass.contains(SrcReg)) {

752

754 SrcReg, M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass);

755 } else if (!M68k::DR16RegClass.contains(SrcReg) &&

756 !M68k::DR32RegClass.contains(SrcReg)) {

757 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");

759 }

760 } else if (FromSR || ToSR) {

762 }

763

764 if (Opc) {

767 return;

768 }

769

770 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "

771 << RI.getName(DstReg) << '\n');

773}

774

775namespace {

779 switch (TRI->getSpillSize(*RC)) {

780 default:

782 dbgs() << "Cannot determine appropriate opcode for load/store to/from "

783 << TRI->getName(Reg) << " of class " << TRI->getRegClassName(RC)

784 << " with spill size " << TRI->getSpillSize(*RC) << '\n');

786 case 2:

787 if (M68k::XR16RegClass.hasSubClassEq(RC))

788 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;

789 if (M68k::DR8RegClass.hasSubClassEq(RC))

790 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;

791 if (M68k::CCRCRegClass.hasSubClassEq(RC))

792 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;

794 case 4:

795 if (M68k::XR32RegClass.hasSubClassEq(RC))

796 return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;

798 }

799}

800

805}

806

811}

812}

813

815 unsigned SubIdx, unsigned &Size,

818

821 return true;

822}

823

830 "Stack slot is too small to store");

831 (void)MFI;

832

835

838}

839

842 Register DstReg, int FrameIndex,

848 "Stack slot is too small to load");

849 (void)MFI;

850

854}

855

856

857

858

859

860

864 if (GlobalBaseReg != 0)

865 return GlobalBaseReg;

866

867

868

869

870

871

872

873

874

875

877 GlobalBaseReg = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);

879 return GlobalBaseReg;

880}

881

882std::pair<unsigned, unsigned>

884 return std::make_pair(TF, 0u);

885}

886

889 using namespace M68kII;

890 static const std::pair<unsigned, const char *> TargetFlags[] = {

891 {MO_ABSOLUTE_ADDRESS, "m68k-absolute"},

892 {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"},

893 {MO_GOT, "m68k-got"},

894 {MO_GOTOFF, "m68k-gotoff"},

895 {MO_GOTPCREL, "m68k-gotpcrel"},

896 {MO_PLT, "m68k-plt"},

897 {MO_TLSGD, "m68k-tlsgd"},

898 {MO_TLSLD, "m68k-tlsld"},

899 {MO_TLSLDM, "m68k-tlsldm"},

900 {MO_TLSIE, "m68k-tlsie"},

901 {MO_TLSLE, "m68k-tlsle"}};

902 return ArrayRef(TargetFlags);

903}

904

905#undef DEBUG_TYPE

906#define DEBUG_TYPE "m68k-create-global-base-reg"

907

908#define PASS_NAME "M68k PIC Global Base Reg Initialization"

909

910namespace {

911

913 static char ID;

915

916 bool runOnMachineFunction(MachineFunction &MF) override {

919

920 unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();

921

922

923 if (GlobalBaseReg == 0)

924 return false;

925

926

931

932

933 BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)

935

936 return true;

937 }

938

939 void getAnalysisUsage(AnalysisUsage &AU) const override {

942 }

943};

944char M68kGlobalBaseReg::ID = 0;

945}

946

948

950 return new M68kGlobalBaseReg();

951}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

AMDGPU Mark last scratch load

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

const HexagonInstrInfo * TII

This file implements the LivePhysRegs utility for tracking liveness of physical registers.

This file exposes functions that may be used with BuildMI from the MachineInstrBuilder....

static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc)

Definition M68kInstrInfo.cpp:50

static bool Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)

Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register...

Definition M68kInstrInfo.cpp:621

This file contains the M68k implementation of the TargetInstrInfo class.

This file contains the declarations for the code emitter which are useful outside of the emitter itse...

This file declares the M68k specific subclass of MachineFunctionInfo.

This file declares the M68k specific subclass of TargetMachine.

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file defines the make_scope_exit function, which executes user-defined cleanup logic at scope ex...

static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)

static unsigned getStoreRegOpcode(Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)

static unsigned getLoadRegOpcode(Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)

static unsigned getLoadStoreRegOpcode(Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool Load)

static unsigned GetCondBranchFromCond(XCore::CondCode CC)

GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.

Represent the analysis usage information of a pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

FunctionPass class - This class is used to implement most global optimizations.

unsigned getGlobalBaseReg(MachineFunction *MF) const

Return a virtual register initialized with the global base register value.

Definition M68kInstrInfo.cpp:861

const M68kSubtarget & Subtarget

bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const

Move immediate to register.

Definition M68kInstrInfo.cpp:353

bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst, MVT MVTSrc) const

Move from register and extend.

Definition M68kInstrInfo.cpp:472

const M68kRegisterInfo & getRegisterInfo() const

TargetInstrInfo is a superset of MRegister info.

const M68kRegisterInfo RI

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Definition M68kInstrInfo.cpp:251

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

Definition M68kInstrInfo.cpp:888

bool expandPostRAPseudo(MachineInstr &MI) const override

Definition M68kInstrInfo.cpp:636

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition M68kInstrInfo.cpp:282

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition M68kInstrInfo.cpp:688

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

Definition M68kInstrInfo.cpp:883

bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const

Definition M68kInstrInfo.cpp:85

bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override

Definition M68kInstrInfo.cpp:663

bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const

Move across register classes without extension.

Definition M68kInstrInfo.cpp:433

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition M68kInstrInfo.cpp:824

bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsRM) const

Expand all MOVEM pseudos into real MOVEMs.

Definition M68kInstrInfo.cpp:575

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition M68kInstrInfo.cpp:840

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition M68kInstrInfo.cpp:259

bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsPush) const

Push/Pop to/from stack.

Definition M68kInstrInfo.cpp:559

M68kInstrInfo(const M68kSubtarget &STI)

Definition M68kInstrInfo.cpp:45

void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const

Add appropriate ZExt nodes.

Definition M68kInstrInfo.cpp:332

bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned, const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const

Move from memory and extend.

Definition M68kInstrInfo.cpp:522

bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const override

Definition M68kInstrInfo.cpp:814

void AddSExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const

Add appropriate SExt nodes.

Definition M68kInstrInfo.cpp:315

void setGlobalBaseReg(unsigned Reg)

unsigned getGlobalBaseReg() const

const M68kInstrInfo * getInstrInfo() const override

Describe properties that are true of each instruction in the target description file.

LLVM_ABI DebugLoc findDebugLoc(instr_iterator MBBI)

Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineBasicBlock & front() const

const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const

Copy all the implicit operands from OtherMI onto this one.

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Representation of each machine instruction.

LLVM_ABI MachineInstr * removeFromParent()

Unlink 'this' from the containing basic block, and return it without deleting it.

const MachineBasicBlock * getParent() const

LLVM_ABI void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

LLVM_ABI unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

static MachineOperand CreateImm(int64_t Val)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI bool match(StringRef String, SmallVectorImpl< StringRef > *Matches=nullptr, std::string *Error=nullptr) const

matches - Match the regex against a given String.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This namespace holds all of the target specific flags that instruction info tracks.

@ MO_GOTPCREL

On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...

Define some predicates that are used for node matching.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

static M68k::CondCode GetCondFromBranchOpc(unsigned Opcode)

@ Implicit

Not emitted register (e.g. carry, or temporary result).

@ Undef

Value of the register doesn't matter.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

detail::scope_exit< std::decay_t< Callable > > make_scope_exit(Callable &&F)

FunctionPass * createM68kGlobalBaseRegPass()

This pass initializes a global base register for PIC on M68k.

Definition M68kInstrInfo.cpp:949

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionAddr VTableAddr Count

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

@ Ref

The access may reference the value stored in memory.

unsigned getKillRegState(bool B)

ArrayRef(const T &OneElt) -> ArrayRef< T >