MachineRegisterInfo.cpp Source File (original) (raw)

23#include "llvm/Config/llvm-config.h"

33#include

35using namespace llvm;

38 cl::init(true), cl::desc("Enable subregister liveness tracking."));

41void MachineRegisterInfo::Delegate::anchor() {}

44 : MF(MF),

47 : MF->getSubtarget().enableSubRegLiveness()) {

49 VRegInfo.reserve(256);

50 UsedPhysRegMask.resize(NumRegs);

51 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());

52 TheDelegates.clear();

53}

57void

60 VRegInfo[Reg].first = RC;

61}

65 VRegInfo[Reg].first = &RegBank;

66}

72 if (OldRC == RC)

73 return RC;

75 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);

76 if (!NewRC || NewRC == OldRC)

77 return NewRC;

79 return nullptr;

80 MRI.setRegClass(Reg, NewRC);

81 return NewRC;

82}

86 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);

87}

89bool

92 unsigned MinNumRegs) {

94 const LLT ConstrainingRegTy = getType(ConstrainingReg);

96 RegTy != ConstrainingRegTy)

97 return false;

99 if (!ConstrainingRegCB.isNull()) {

101 if (RegCB.isNull())

105 return false;

110 return false;

111 } else if (RegCB != ConstrainingRegCB)

112 return false;

113 }

114 if (ConstrainingRegTy.isValid())

115 setType(Reg, ConstrainingRegTy);

116 return true;

117}

118

119bool

125

126

127 if (NewRC == OldRC)

128 return false;

129

130

132

134 unsigned OpNo = &MO - &MI->getOperand(0);

135 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, TRI);

136 if (!NewRC || NewRC == OldRC)

137 return false;

138 }

140 return true;

141}

142

145 VRegInfo.grow(Reg);

147 return Reg;

148}

149

150

151

152

156 assert(RegClass && "Cannot create register without RegClass!");

158 "Virtual register RegClass must be allocatable.");

159

160

162 VRegInfo[Reg].first = RegClass;

164 return Reg;

165}

166

170 VRegInfo[Reg].first = RegAttr.RCOrRB;

173 return Reg;

174}

175

179 VRegInfo[Reg].first = VRegInfo[VReg].first;

182 return Reg;

183}

184

186 VRegToType.grow(VReg);

187 VRegToType[VReg] = Ty;

188}

189

192

194

195 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);

198 return Reg;

199}

200

202

203

205#ifndef NDEBUG

206 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {

208 if (!VRegInfo[Reg].second)

209 continue;

211 errs() << "Remaining virtual register "

214 errs() << "...in instruction: " << MI << "\n";

215 std::abort();

216 }

217#endif

218 VRegInfo.clear();

219 for (auto &I : LiveIns)

220 I.second = 0;

221}

222

224#ifndef NDEBUG

225 bool Valid = true;

229 if () {

231 << " use list MachineOperand " << MO

232 << " has no parent instruction.\n";

233 Valid = false;

234 continue;

235 }

237 unsigned NumOps = MI->getNumOperands();

238 if (!(MO >= MO0 && MO < MO0+NumOps)) {

240 << " use list MachineOperand " << MO

241 << " doesn't belong to parent MI: " << *MI;

242 Valid = false;

243 }

244 if (!MO->isReg()) {

246 << " MachineOperand " << MO << ": " << *MO

247 << " is not a register\n";

248 Valid = false;

249 }

250 if (MO->getReg() != Reg) {

252 << " use-list MachineOperand " << MO << ": "

253 << *MO << " is the wrong register\n";

254 Valid = false;

255 }

256 }

257 assert(Valid && "Invalid use list");

258#endif

259}

260

262#ifndef NDEBUG

263 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)

267#endif

268}

269

270

272 assert(!MO->isOnRegUseList() && "Already on list");

275

276

277

278

279

280

281 if (!Head) {

282 MO->Contents.Reg.Prev = MO;

283 MO->Contents.Reg.Next = nullptr;

284 HeadRef = MO;

285 return;

286 }

287 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");

288

289

291 assert(Last && "Inconsistent use list");

292 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");

293 Head->Contents.Reg.Prev = MO;

294 MO->Contents.Reg.Prev = Last;

295

296

297

298 if (MO->isDef()) {

299

300 MO->Contents.Reg.Next = Head;

301 HeadRef = MO;

302 } else {

303

304 MO->Contents.Reg.Next = nullptr;

305 Last->Contents.Reg.Next = MO;

306 }

307}

308

309

311 assert(MO->isOnRegUseList() && "Operand not on use list");

314 assert(Head && "List already empty");

315

316

319

320

321 if (MO == Head)

322 HeadRef = Next;

323 else

324 Prev->Contents.Reg.Next = Next;

325

326 (Next ? Next : Head)->Contents.Reg.Prev = Prev;

327

328 MO->Contents.Reg.Prev = nullptr;

329 MO->Contents.Reg.Next = nullptr;

330}

331

332

333

334

335

336

337

338

342 assert(Src != Dst && NumOps && "Noop moveOperands");

343

344

345 int Stride = 1;

346 if (Dst >= Src && Dst < Src + NumOps) {

347 Stride = -1;

350 }

351

352

353 do {

355

356

357 if (Src->isReg()) {

358 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());

361 assert(Head && "List empty, but operand is chained");

362 assert(Prev && "Operand was not on use-def list");

363

364

365

366 if (Src == Head)

367 Head = Dst;

368 else

369 Prev->Contents.Reg.Next = Dst;

370

371

372

373 (Next ? Next : Head)->Contents.Reg.Prev = Dst;

374 }

375

376 Dst += Stride;

377 Src += Stride;

379}

380

381

382

383

384

385

387 assert(FromReg != ToReg && "Cannot replace a reg with itself");

388

390

391

394 O.substPhysReg(ToReg, *TRI);

395 } else {

396 O.setReg(ToReg);

397 }

398 }

399}

400

401

402

403

405

408 return nullptr;

410 "getVRegDef assumes at most one definition");

411 return &*I;

412}

413

414

415

416

418 if (def_empty(Reg)) return nullptr;

421 return nullptr;

422 return &*I;

423}

424

428

432

435 return hasSingleElement(RegNoDbgUses) ? &*RegNoDbgUses.begin() : nullptr;

436}

437

440 return hasSingleElement(RegNoDbgUsers) ? &*RegNoDbgUsers.begin() : nullptr;

441}

442

444 unsigned MaxUsers) const {

446 MaxUsers);

447}

448

449

450

451

452

455 MO.setIsKill(false);

456}

457

459 for (const std::pair<MCRegister, Register> &LI : liveins())

460 if ((Register)LI.first == Reg || LI.second == Reg)

461 return true;

462 return false;

463}

464

465

466

468 for (const std::pair<MCRegister, Register> &LI : liveins())

469 if (LI.second == VReg)

470 return LI.first;

472}

473

474

475

477 for (const std::pair<MCRegister, Register> &LI : liveins())

478 if (LI.first == PReg)

479 return LI.second;

481}

482

483

484

485void

489

490 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)

491 if (LiveIns[i].second) {

493

494

495

496

497

498 LiveIns.erase(LiveIns.begin() + i);

499 --i; --e;

500 } else {

501

503 TII.get(TargetOpcode::COPY), LiveIns[i].second)

504 .addReg(LiveIns[i].first);

505

506

507 EntryMBB->addLiveIn(LiveIns[i].first);

508 }

509 } else {

510

511 EntryMBB->addLiveIn(LiveIns[i].first);

512 }

513}

514

516

517 assert(Reg.isVirtual());

520}

521

522#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

527#endif

528

532 "Invalid ReservedRegs vector from target");

533}

534

537

539 if (TRI->isConstantPhysReg(PhysReg))

540 return true;

541

542

543

547 return false;

548 return true;

549}

550

551

552

553

555

556

558 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))

559 UseMI.setDebugValueUndef();

560 }

561}

562

565 if (!MO.isGlobal())

566 continue;

568 if (Func != nullptr)

569 return Func;

570 }

571 return nullptr;

572}

573

575

577 if (.isCall())

578 return false;

580 if ( MBB .succ_empty())

581 return false;

583

584

586 return false;

588 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||

590}

591

593 bool SkipNoReturnDef) const {

594 if (UsedPhysRegMask.test(PhysReg.id()))

595 return true;

600 continue;

601 return true;

602 }

603 }

604 return false;

605}

606

608 bool SkipRegMaskTest) const {

609 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg.id()))

610 return true;

613 ++AliasReg) {

615 return true;

616 }

617 return false;

618}

619

621

624 "Trying to disable an invalid register");

625

626 if (!IsUpdatedCSRsInitialized) {

627 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);

629 UpdatedCSRs.push_back(*I);

630

631

632

633 UpdatedCSRs.push_back(0);

634

635 IsUpdatedCSRsInitialized = true;

636 }

637

638

641}

642

644 if (IsUpdatedCSRsInitialized)

645 return UpdatedCSRs.data();

646

648

649 for (unsigned I = 0; Regs[I]; ++I)

650 if (MF->getSubtarget().isRegisterReservedByUser(Regs[I]))

651 MF->getRegInfo().disableCalleeSavedRegister(Regs[I]);

652

653 return Regs;

654}

655

657 if (IsUpdatedCSRsInitialized)

658 UpdatedCSRs.clear();

659

661

662

663

664 UpdatedCSRs.push_back(0);

665 IsUpdatedCSRsInitialized = true;

666}

667

671 if (all_of(TRI->superregs_inclusive(*Root),

672 [&](MCPhysReg Super) { return isReserved(Super); }))

673 return true;

674 }

675 return false;

676}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file contains the simple types necessary to represent the attributes associated with functions a...

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

const HexagonInstrInfo * TII

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))

static bool isNoReturnDef(const MachineOperand &MO)

Definition MachineRegisterInfo.cpp:574

static const TargetRegisterClass * constrainRegClass(MachineRegisterInfo &MRI, Register Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs)

Definition MachineRegisterInfo.cpp:69

Promote Memory to Register

static const Function * getCalledFunction(const Value *V)

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

constexpr bool isValid() const

MCRegAliasIterator enumerates all registers aliasing Reg.

MCRegUnitRootIterator enumerates the root registers of a register unit.

bool isValid() const

Check if the iterator is at the end of the list.

unsigned getNumRegs() const

Return the number of registers this target has (useful for sizing arrays holding per register informa...

Wrapper class representing physical registers. Should be passed by value.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

constexpr unsigned id() const

void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())

Adds the specified register as a live in.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI void verifyUseList(Register Reg) const

Verify the sanity of the use list for Reg.

Definition MachineRegisterInfo.cpp:223

LLVM_ABI bool hasOneNonDBGUse(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.

Definition MachineRegisterInfo.cpp:425

void insertVRegByName(StringRef Name, Register Reg)

LLVM_ABI void verifyUseLists() const

Verify the use list of all registers.

Definition MachineRegisterInfo.cpp:261

LLVM_ABI void markUsesInDebugValueAsUndef(Register Reg) const

markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...

Definition MachineRegisterInfo.cpp:554

iterator_range< reg_iterator > reg_operands(Register Reg) const

LLVM_ABI bool recomputeRegClass(Register Reg)

recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...

Definition MachineRegisterInfo.cpp:120

LLVM_ABI void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

Definition MachineRegisterInfo.cpp:529

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

LLVM_ABI void clearKillFlags(Register Reg) const

clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...

Definition MachineRegisterInfo.cpp:453

LLVM_ABI MachineRegisterInfo(MachineFunction *MF)

Definition MachineRegisterInfo.cpp:43

LLVM_ABI MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

Definition MachineRegisterInfo.cpp:404

iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const

LLVM_ABI void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)

EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.

Definition MachineRegisterInfo.cpp:486

bool use_nodbg_empty(Register RegNo) const

use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.

const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const

Return the register bank or register class of Reg.

LLVM_ABI MachineOperand * getOneNonDBGUse(Register RegNo) const

If the register has a single non-Debug use, returns it; otherwise returns nullptr.

Definition MachineRegisterInfo.cpp:433

static def_instr_iterator def_instr_end()

LLVM_ABI void dumpUses(Register RegNo) const

Definition MachineRegisterInfo.cpp:523

LLVM_ABI void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)

Move NumOps operands from Src to Dst, updating use-def lists as needed.

Definition MachineRegisterInfo.cpp:339

def_iterator def_begin(Register RegNo) const

defusechain_instr_iterator< false, true, false, true > def_instr_iterator

def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...

void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

Definition MachineRegisterInfo.cpp:154

def_instr_iterator def_instr_begin(Register RegNo) const

LLT getType(Register Reg) const

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

bool def_empty(Register RegNo) const

def_empty - Return true if there are no instructions defining the specified register (it may be live-...

LLVM_ABI bool isLiveIn(Register Reg) const

Definition MachineRegisterInfo.cpp:458

bool reg_nodbg_empty(Register RegNo) const

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const

ArrayRef< std::pair< MCRegister, Register > > liveins() const

LLVM_ABI bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const

hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.

Definition MachineRegisterInfo.cpp:443

LLVM_ABI bool hasOneNonDBGUser(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...

Definition MachineRegisterInfo.cpp:429

LLVM_ABI void clearVirtRegs()

clearVirtRegs - Remove all virtual registers (after physreg assignment).

Definition MachineRegisterInfo.cpp:204

LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")

Creates a new virtual register that has no register class, register bank or size assigned yet.

Definition MachineRegisterInfo.cpp:143

bool isAllocatable(MCRegister PhysReg) const

isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...

LLVM_ABI void setRegBank(Register Reg, const RegisterBank &RegBank)

Set the register bank to RegBank for Reg.

Definition MachineRegisterInfo.cpp:63

LLVM_ABI MCRegister getLiveInPhysReg(Register VReg) const

getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...

Definition MachineRegisterInfo.cpp:467

LLVM_ABI const MCPhysReg * getCalleeSavedRegs() const

Returns list of callee saved registers.

Definition MachineRegisterInfo.cpp:643

iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const

LLVM_ABI void setType(Register VReg, LLT Ty)

Set the low-level type of VReg to Ty.

Definition MachineRegisterInfo.cpp:185

LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC)

setRegClass - Set the register class of the specified virtual register.

Definition MachineRegisterInfo.cpp:58

LLVM_ABI Register createGenericVirtualRegister(LLT Ty, StringRef Name="")

Create and return a new generic virtual register with low-level type Ty.

Definition MachineRegisterInfo.cpp:191

LLVM_ABI bool isReservedRegUnit(MCRegUnit Unit) const

Returns true when the given register unit is considered reserved.

Definition MachineRegisterInfo.cpp:668

LLVM_ABI void clearVirtRegTypes()

Remove all types associated to virtual registers (after instruction selection and constraining of all...

Definition MachineRegisterInfo.cpp:201

LLVM_ABI Register getLiveInVirtReg(MCRegister PReg) const

getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...

Definition MachineRegisterInfo.cpp:476

static def_iterator def_end()

LLVM_ABI void disableCalleeSavedRegister(MCRegister Reg)

Disables the register from the list of CSRs.

Definition MachineRegisterInfo.cpp:620

iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const

void noteNewVirtualRegister(Register Reg)

LLVM_ABI void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)

Sets the updated Callee Saved Registers list.

Definition MachineRegisterInfo.cpp:656

iterator_range< use_instr_iterator > use_instructions(Register Reg) const

const TargetRegisterInfo * getTargetRegisterInfo() const

LLVM_ABI LaneBitmask getMaxLaneMaskForVReg(Register Reg) const

Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...

Definition MachineRegisterInfo.cpp:515

LLVM_ABI bool isConstantPhysReg(MCRegister PhysReg) const

Returns true if PhysReg is unallocatable and constant throughout the function.

Definition MachineRegisterInfo.cpp:535

iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const

LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name="")

Create and return a new virtual register in the function with the same attributes as the given regist...

Definition MachineRegisterInfo.cpp:176

LLVM_ABI bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)

Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...

Definition MachineRegisterInfo.cpp:90

LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)

constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...

Definition MachineRegisterInfo.cpp:84

void noteCloneVirtualRegister(Register NewReg, Register SrcReg)

iterator_range< use_iterator > use_operands(Register Reg) const

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

LLVM_ABI void removeRegOperandFromUseList(MachineOperand *MO)

Remove MO from its use-def list.

Definition MachineRegisterInfo.cpp:310

LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg)

replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.

Definition MachineRegisterInfo.cpp:386

LLVM_ABI bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const

Return true if the specified register is modified in this function.

Definition MachineRegisterInfo.cpp:592

LLVM_ABI void addRegOperandToUseList(MachineOperand *MO)

Add MO to the linked list of operands for its register.

Definition MachineRegisterInfo.cpp:271

LLVM_ABI MachineInstr * getOneNonDBGUser(Register RegNo) const

If the register has a single non-Debug instruction using the specified register, returns it; otherwis...

Definition MachineRegisterInfo.cpp:438

LLVM_ABI MachineInstr * getUniqueVRegDef(Register Reg) const

getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...

Definition MachineRegisterInfo.cpp:417

static use_instr_nodbg_iterator use_instr_nodbg_end()

LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const

Return true if the specified register is modified or read in this function.

Definition MachineRegisterInfo.cpp:607

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

unsigned getNumRegs() const

Return the number of registers in this class.

bool isAllocatable() const

Return true if this register class may be used to create virtual registers.

LaneBitmask getLaneMask() const

Returns the combination of all lane masks of register in this class.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual BitVector getReservedRegs(const MachineFunction &MF) const =0

Returns a bitset indexed by physical register number indicating if a register is a special register t...

virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0

Return a null-terminated list of all of the callee-saved registers on this target.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

void append_range(Container &C, Range &&R)

Wrapper function to append range R to container C.

bool hasNItemsOrLess(IterTy &&Begin, IterTy &&End, unsigned N, Pred &&ShouldBeCounted=[](const decltype(*std::declval< IterTy >()) &) { return true;})

Returns true if the sequence [Begin, End) has N or less items.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

void erase(Container &C, ValueType V)

Wrapper function to remove a value from a container:

bool hasSingleElement(ContainerTy &&C)

Returns true if the given container only contains a single element.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

FunctionAddr VTableAddr Next

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

All attributes(register class or bank and low-level type) a virtual register can have.