MachineUniformityAnalysis.cpp Source File (original) (raw)

19using namespace llvm;

21template <>

24 for (auto &op : I.all_defs()) {

26 return true;

27 }

28 return false;

29}

31template <>

34 bool insertedDivergent = false;

35 const auto &MRI = F.getRegInfo();

36 const auto &RBI = *F.getSubtarget().getRegBankInfo();

37 const auto &TRI = *MRI.getTargetRegisterInfo();

38 for (auto &op : Instr.all_defs()) {

39 if (.getReg().isVirtual())

40 continue;

42 if (TRI.isUniformReg(MRI, RBI, op.getReg()))

43 continue;

45 }

46 return insertedDivergent;

47}

49template <>

51 const auto &InstrInfo = *F.getSubtarget().getInstrInfo();

55 auto uniformity = InstrInfo.getInstructionUniformity(instr);

60 break;

63 break;

65 break;

66 }

67 }

68 }

69}

71template <>

72void llvm::GenericUniformityAnalysisImpl::pushUsers(

74 assert(isDivergent(Reg));

75 const auto &RegInfo = F.getRegInfo();

76 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) {

77 markDivergent(UserInstr);

78 }

79}

81template <>

82void llvm::GenericUniformityAnalysisImpl::pushUsers(

84 assert(!isAlwaysUniform(Instr));

85 if (Instr.isTerminator())

86 return;

88 auto Reg = op.getReg();

89 if (isDivergent(Reg))

90 pushUsers(Reg);

91 }

92}

94template <>

95bool llvm::GenericUniformityAnalysisImpl::usesValueFromCycle(

97 assert(!isAlwaysUniform(I));

98 for (auto &Op : I.operands()) {

99 if (.isReg() || .readsReg())

100 continue;

101 auto Reg = Op.getReg();

102

103

104

105 if (Reg.isPhysical())

106 return true;

107

108 auto *Def = F.getRegInfo().getVRegDef(Reg);

110 return true;

111 }

112 return false;

113}

114

115template <>

119 const auto &RegInfo = F.getRegInfo();

120 for (auto &Op : I.all_defs()) {

121 if (.getReg().isVirtual())

122 continue;

123 auto Reg = Op.getReg();

125 if (DefCycle.contains(UserInstr.getParent()))

126 continue;

127 markDivergent(UserInstr);

128

129 recordTemporalDivergence(Reg, &UserInstr, &DefCycle);

130 }

131 }

132}

133

134template <>

137 if (!U.isReg())

138 return false;

139

140 auto Reg = U.getReg();

142 return true;

143

144 const auto &RegInfo = F.getRegInfo();

145 auto *Def = RegInfo.getOneDef(Reg);

146 if (!Def)

147 return true;

148

149 auto *DefInstr = Def->getParent();

150 auto *UseInstr = U.getParent();

151 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr);

152}

153

154

155

159

163 assert(F.getRegInfo().isSSA() && "Expected to be run on SSA form!");

165 if (HasBranchDivergence)

167 return UI;

168}

169

170namespace {

171

173public:

174 static char ID;

175

176 MachineUniformityInfoPrinterPass();

177

179 void getAnalysisUsage(AnalysisUsage &AU) const override;

180};

181

182}

183

184AnalysisKey MachineUniformityAnalysis::Key;

185

192 .getManager();

196 TTI.hasBranchDivergence(&F));

197}

198

203 OS << "MachineUniformityInfo for function: ";

205 OS << '\n';

206 MUI.print(OS);

208}

209

211

216

218 "Machine Uniformity Info Analysis", false, true)

222 "Machine Uniformity Info Analysis", false, true)

223

225 AU.setPreservesAll();

229}

230

234

235

237 return false;

238}

239

241 const Module *) const {

242 OS << "MachineUniformityInfo for function: ";

243 UI.getFunction().getFunction().printAsOperand(OS, false);

244 OS << '\n';

245 UI.print(OS);

246}

247

248char MachineUniformityInfoPrinterPass::ID = 0;

249

250MachineUniformityInfoPrinterPass::MachineUniformityInfoPrinterPass()

254}

255

257 "print-machine-uniformity",

258 "Print Machine Uniformity Info Analysis", true, true)

261 "print-machine-uniformity",

262 "Print Machine Uniformity Info Analysis", true, true)

263

264void MachineUniformityInfoPrinterPass::getAnalysisUsage(

266 AU.setPreservesAll();

269}

270

271bool MachineUniformityInfoPrinterPass::runOnMachineFunction(

273 auto &UI = getAnalysis();

274 UI.print(errs());

275 return false;

276}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Implementation of uniformity analysis.

This file declares a specialization of the GenericSSAContext template class for Machine IR.

Machine IR instance of the generic uniformity analysis.

FunctionAnalysisManager FAM

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This pass exposes codegen information to IR-level passes.

unify loop Fixup each natural loop to have a single exit block

PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)

Get the result of an analysis pass for a given IR unit.

Represent the analysis usage information of a pass.

bool contains(const BlockT *Block) const

Return whether Block is contained in the cycle.

Analysis that identifies uniform values in a data-parallel execution.

bool isDivergentUse(const UseT &U) const

bool hasDivergentDefs(const InstructionT &I) const

bool markDefsDivergent(const InstructionT &Instr)

Mark outputs of Instr as divergent.

bool isDivergent(const InstructionT &I) const

void markDivergent(const InstructionT &I)

Examine I for divergent outputs and add to the worklist.

void addUniformOverride(const InstructionT &Instr)

Mark UniVal as a value that is always uniform.

Legacy analysis pass which computes a MachineCycleInfo.

Analysis pass which computes a MachineDominatorTree.

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

MachineFunctionPass(char &ID)

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

Legacy analysis pass which computes a MachineUniformityInfo.

MachineUniformityAnalysisPass()

Definition MachineUniformityAnalysis.cpp:212

void print(raw_ostream &OS, const Module *M=nullptr) const override

print - Print out the internal state of the pass.

Definition MachineUniformityAnalysis.cpp:240

bool runOnMachineFunction(MachineFunction &F) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

Definition MachineUniformityAnalysis.cpp:231

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition MachineUniformityAnalysis.cpp:224

Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition MachineUniformityAnalysis.cpp:187

MachineUniformityInfo Result

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition MachineUniformityAnalysis.cpp:200

A Module instance is used to store all the information related to an LLVM module.

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

AnalysisType & getAnalysis() const

getAnalysis() - This function is used by subclasses to get to the analysis information ...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

Analysis pass providing the TargetTransformInfo.

LLVM_ABI void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const

Print the name of this Value out to the specified raw_ostream.

This class implements an extremely fast bulk output stream that can only output to a stream.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

NodeAddr< DefNode * > Def

NodeAddr< InstrNode * > Instr

This is an optimization pass for GlobalISel generic memory operations.

GenericUniformityInfo< MachineSSAContext > MachineUniformityInfo

LLVM_ABI void initializeMachineUniformityAnalysisPassPass(PassRegistry &)

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

DWARFExpression::Operation Op

MachineUniformityInfo computeMachineUniformityInfo(MachineFunction &F, const MachineCycleInfo &cycleInfo, const MachineDominatorTree &domTree, bool HasBranchDivergence)

Compute uniformity information for a Machine IR function.

Definition MachineUniformityAnalysis.cpp:160

@ AlwaysUniform

The result values are always uniform.

@ NeverUniform

The result values can never be assumed to be uniform.

@ Default

The result values are uniform if and only if all operands are uniform.

GenericCycleInfo< MachineSSAContext > MachineCycleInfo

MachineCycleInfo::CycleT MachineCycle

LLVM_ABI void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &)

A special type used by analysis passes to provide an address that identifies that particular analysis...