MicroMipsSizeReduction.cpp Source File (original) (raw)

20using namespace llvm;

22#define DEBUG_TYPE "micromips-reduce-size"

23#define MICROMIPS_SIZE_REDUCE_NAME "MicroMips instruction size reduce pass"

25 STATISTIC(NumReduced, "Number of instructions reduced (32-bit to 16-bit ones, "

26 "or two instructions into one");

28namespace {

32enum OperandTransfer {

33 OT_NA,

34 OT_OperandsAll,

35 OT_Operands02,

36 OT_Operand2,

37 OT_OperandsXOR,

38 OT_OperandsLwp,

39 OT_OperandsSwp,

40 OT_OperandsMovep,

41};

45enum ReduceType {

46 RT_TwoInstr,

47 RT_OneInstr

48};

51struct ImmField {

52 ImmField() : ImmFieldOperand(-1), Shift(0), LBound(0), HBound(0) {}

53 ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,

54 int8_t ImmFieldOperand)

55 : ImmFieldOperand(ImmFieldOperand), Shift(Shift), LBound(LBound),

56 HBound(HBound) {}

57 int8_t ImmFieldOperand;

58 uint8_t Shift;

59 int16_t LBound;

60 int16_t HBound;

61};

65struct OpInfo {

66 OpInfo(enum OperandTransfer TransferOperands)

67 : TransferOperands(TransferOperands) {}

68 OpInfo() : TransferOperands(OT_NA) {}

70 enum OperandTransfer

71 TransferOperands;

72};

75struct OpCodes {

76 OpCodes(unsigned WideOpc, unsigned NarrowOpc)

77 : WideOpc(WideOpc), NarrowOpc(NarrowOpc) {}

79 unsigned WideOpc;

80 unsigned NarrowOpc;

81};

83typedef struct ReduceEntryFunArgs ReduceEntryFunArgs;

87struct ReduceEntry {

89 enum ReduceType eRType;

90 bool (*ReduceFunction)(

91 ReduceEntryFunArgs *Arguments);

92 struct OpCodes Ops;

93 struct OpInfo OpInf;

94 struct ImmField Imm;

96 ReduceEntry(enum ReduceType RType, struct OpCodes Op,

97 bool (*F)(ReduceEntryFunArgs *Arguments), struct OpInfo OpInf,

98 struct ImmField Imm)

99 : eRType(RType), ReduceFunction(F), Ops(Op), OpInf(OpInf), Imm(Imm) {}

100

101 unsigned NarrowOpc() const { return Ops.NarrowOpc; }

102 unsigned WideOpc() const { return Ops.WideOpc; }

103 int16_t LBound() const { return Imm.LBound; }

104 int16_t HBound() const { return Imm.HBound; }

105 uint8_t Shift() const { return Imm.Shift; }

106 int8_t ImmField() const { return Imm.ImmFieldOperand; }

107 enum OperandTransfer TransferOperands() const {

108 return OpInf.TransferOperands;

109 }

110 enum ReduceType RType() const { return eRType; }

111

112

113 bool operator<(const unsigned int r) const { return (WideOpc() < r); }

114

115

116 friend bool operator<(const unsigned int r, const struct ReduceEntry &re) {

117 return (r < re.WideOpc());

118 }

119};

120

121

122struct ReduceEntryFunArgs {

124 const ReduceEntry &Entry;

126 &NextMII;

127

128 ReduceEntryFunArgs(MachineInstr *argMI, const ReduceEntry &argEntry,

130 : MI(argMI), Entry(argEntry), NextMII(argNextMII) {}

131};

132

134

136public:

137 static char ID;

138 MicroMipsSizeReduce();

139

142

144

146 return "microMIPS instruction size reduction pass";

147 }

148

149private:

150

152

153

156

157

158

159 static bool ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments);

160

161

162

163 static bool ReduceXWtoXWP(ReduceEntryFunArgs *Arguments);

164

165

166

167 static bool ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments);

168

169

170

171 static bool ReduceSXtoSX16(ReduceEntryFunArgs *Arguments);

172

173

174

175 static bool ReduceMoveToMovep(ReduceEntryFunArgs *Arguments);

176

177

178 static bool ReduceArithmeticInstructions(ReduceEntryFunArgs *Arguments);

179

180

181

182 static bool ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments);

183

184

185

186 static bool ReduceADDIUToADDIUR1SP(ReduceEntryFunArgs *Arguments);

187

188

189

190 static bool ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments);

191

192

193

194

195

196 static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry,

198 bool ConsecutiveForward = true);

199

200

201 static ReduceEntryVector ReduceTable;

202};

203

204char MicroMipsSizeReduce::ID = 0;

206

207

208

209ReduceEntryVector MicroMipsSizeReduce::ReduceTable = {

210

211

212

213

214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),

215 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},

216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,

217 OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},

218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),

219 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},

220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),

221 ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},

222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),

223 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),

224 ImmField(0, 0, 0, -1)},

225 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),

226 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),

227 ImmField(0, 0, 0, -1)},

228 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,

229 OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},

230 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,

231 OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},

232 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),

233 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},

234 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu_MM, Mips::ADDIUR1SP_MM),

235 ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},

236 {RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,

237 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},

238 {RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,

239 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},

240 {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,

241 OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},

242 {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,

243 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},

244 {RT_TwoInstr, OpCodes(Mips::LW16_MM, Mips::LWP_MM), ReduceXWtoXWP,

245 OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},

246 {RT_TwoInstr, OpCodes(Mips::LW_MM, Mips::LWP_MM), ReduceXWtoXWP,

247 OpInfo(OT_OperandsLwp), ImmField(0, -2048, 2048, 2)},

248 {RT_OneInstr, OpCodes(Mips::LW_MM, Mips::LWSP_MM), ReduceXWtoXWSP,

249 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},

250 {RT_TwoInstr, OpCodes(Mips::MOVE16_MM, Mips::MOVEP_MM), ReduceMoveToMovep,

251 OpInfo(OT_OperandsMovep), ImmField(0, 0, 0, -1)},

252 {RT_OneInstr, OpCodes(Mips::SB, Mips::SB16_MM), ReduceSXtoSX16,

253 OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},

254 {RT_OneInstr, OpCodes(Mips::SB_MM, Mips::SB16_MM), ReduceSXtoSX16,

255 OpInfo(OT_OperandsAll), ImmField(0, 0, 16, 2)},

256 {RT_OneInstr, OpCodes(Mips::SH, Mips::SH16_MM), ReduceSXtoSX16,

257 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},

258 {RT_OneInstr, OpCodes(Mips::SH_MM, Mips::SH16_MM), ReduceSXtoSX16,

259 OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},

260 {RT_OneInstr, OpCodes(Mips::SUBu, Mips::SUBU16_MM),

261 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),

262 ImmField(0, 0, 0, -1)},

263 {RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),

264 ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),

265 ImmField(0, 0, 0, -1)},

266 {RT_TwoInstr, OpCodes(Mips::SW, Mips::SWP_MM), ReduceXWtoXWP,

267 OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},

268 {RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,

269 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},

270 {RT_TwoInstr, OpCodes(Mips::SW16_MM, Mips::SWP_MM), ReduceXWtoXWP,

271 OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},

272 {RT_TwoInstr, OpCodes(Mips::SW_MM, Mips::SWP_MM), ReduceXWtoXWP,

273 OpInfo(OT_OperandsSwp), ImmField(0, -2048, 2048, 2)},

274 {RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,

275 OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},

276 {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,

277 OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},

278 {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,

279 OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};

280}

281

283 false, false)

284

285

287 if (MO.isReg() && ((MO.getReg() == Mips::SP)))

288 return true;

289 return false;

290}

291

292

294 if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))

295 return true;

296 return false;

297}

298

299

301 if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))

302 return true;

303 return false;

304}

305

306

307

309

310 if (->getOperand(Op).isImm())

311 return false;

312 Imm = MI->getOperand(Op).getImm();

313 return true;

314}

315

316

318 int64_t Value2 = Value >> 2;

319 if (((Value & (int64_t)maskTrailingZeros<uint64_t>(2)) == Value) &&

320 ((Value2 >= 2 && Value2 <= 257) || (Value2 >= -258 && Value2 <= -3)))

321 return true;

322 return false;

323}

324

325

326

327static bool InRange(int64_t Value, unsigned short Shift, int LBound,

328 int HBound) {

329 int64_t Value2 = Value >> Shift;

330 if (((Value & (int64_t)maskTrailingZeros<uint64_t>(Shift)) == Value) &&

331 (Value2 >= LBound) && (Value2 < HBound))

332 return true;

333 return false;

334}

335

336

338

339 int64_t offset;

340

341 if ( GetImm (MI, Entry.ImmField(), offset))

342 return false;

343

344 if ( InRange (offset, Entry.Shift(), Entry.LBound(), Entry.HBound()))

345 return false;

346

347 return true;

348}

349

350

352 const ReduceEntry &Entry) {

353

354 if (ReduceToLwp &&

355 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM ||

356 MI->getOpcode() == Mips::LW16_MM))

357 return false;

358

359 if (!ReduceToLwp &&

360 !(MI->getOpcode() == Mips::SW || MI->getOpcode() == Mips::SW_MM ||

361 MI->getOpcode() == Mips::SW16_MM))

362 return false;

363

364 Register reg = MI->getOperand(0).getReg();

365 if (reg == Mips::RA)

366 return false;

367

369 return false;

370

371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))

372 return false;

373

374 return true;

375}

376

377

379 constexpr std::array<unsigned, 31> Registers = {

380 {Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,

381 Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,

382 Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,

383 Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP,

384 Mips::SP, Mips::FP, Mips::RA}};

385

389 return true;

390 else

391 return false;

392 }

393 }

394 return false;

395}

396

397

399

400 int64_t Offset1, Offset2;

401 if ( GetImm (MI1, 2, Offset1))

402 return false;

403 if ( GetImm (MI2, 2, Offset2))

404 return false;

405

408

410}

411

413

416

418 unsigned Opcode = MI->getOpcode();

419

420

421 ReduceEntryVector::const_iterator Start = std::begin(ReduceTable);

422 ReduceEntryVector::const_iterator End = std::end(ReduceTable);

423

424 std::pair<ReduceEntryVector::const_iterator,

425 ReduceEntryVector::const_iterator>

426 Range = std::equal_range(Start, End, Opcode);

427

429 return false;

430

431 for (ReduceEntryVector::const_iterator Entry = Range.first;

432 Entry != Range.second; ++Entry) {

433 ReduceEntryFunArgs Arguments(&(*MII), *Entry, NextMII);

434 if (((*Entry).ReduceFunction)(&Arguments))

435 return true;

436 }

437 return false;

438}

439

440bool MicroMipsSizeReduce::ReduceXWtoXWSP(ReduceEntryFunArgs *Arguments) {

441

444

446 return false;

447

448 if (!IsSP(MI->getOperand(1)))

449 return false;

450

451 return ReplaceInstruction(MI, Entry);

452}

453

454bool MicroMipsSizeReduce::ReduceXWtoXWP(ReduceEntryFunArgs *Arguments) {

455

459 Arguments->MI->getParent()->instr_end();

460

461 if (NextMII == E)

462 return false;

463

466

467

468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) ||

469 (MI1->getOpcode() == Mips::LW_MM) ||

470 (MI1->getOpcode() == Mips::LW16_MM);

471

473 return false;

474

476 return false;

477

480

481 if (Reg1 != Reg2)

482 return false;

483

486

487 if (!(ConsecutiveForward || ConsecutiveBackward))

488 return false;

489

490 NextMII = std::next(NextMII);

491 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);

492}

493

494bool MicroMipsSizeReduce::ReduceArithmeticInstructions(

496

499

503 return false;

504

505 return ReplaceInstruction(MI, Entry);

506}

507

508bool MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(

510

513

515 return false;

516

518 return false;

519

520 return ReplaceInstruction(MI, Entry);

521}

522

523bool MicroMipsSizeReduce::ReduceADDIUToADDIUSP(ReduceEntryFunArgs *Arguments) {

524

527

528 int64_t ImmValue;

530 return false;

531

533 return false;

534

535 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))

536 return false;

537

538 return ReplaceInstruction(MI, Entry);

539}

540

541bool MicroMipsSizeReduce::ReduceLXUtoLXU16(ReduceEntryFunArgs *Arguments) {

542

545

547 return false;

548

551 return false;

552

553 return ReplaceInstruction(MI, Entry);

554}

555

556bool MicroMipsSizeReduce::ReduceSXtoSX16(ReduceEntryFunArgs *Arguments) {

557

560

562 return false;

563

566 return false;

567

568 return ReplaceInstruction(MI, Entry);

569}

570

571

572

574

575 if (Reg == Mips::ZERO || Reg == Mips::V0 || Reg == Mips::V1 ||

576 Reg == Mips::S0 || Reg == Mips::S1 || Reg == Mips::S2 ||

577 Reg == Mips::S3 || Reg == Mips::S4)

578 return true;

579

580 return false;

581}

582

583

584

586

587 if (Reg == Mips::A0 || Reg == Mips::A1 || Reg == Mips::A2 ||

588 Reg == Mips::A3 || Reg == Mips::S5 || Reg == Mips::S6)

589 return true;

590

591 return false;

592}

593

594

595

597

598 if ((R0 == Mips::A0 && R1 == Mips::S5) ||

599 (R0 == Mips::A0 && R1 == Mips::S6) ||

600 (R0 == Mips::A0 && R1 == Mips::A1) ||

601 (R0 == Mips::A0 && R1 == Mips::A2) ||

602 (R0 == Mips::A0 && R1 == Mips::A3) ||

603 (R0 == Mips::A1 && R1 == Mips::A2) ||

604 (R0 == Mips::A1 && R1 == Mips::A3) ||

605 (R0 == Mips::A2 && R1 == Mips::A3))

606 return true;

607

608 return false;

609}

610

611bool MicroMipsSizeReduce::ReduceMoveToMovep(ReduceEntryFunArgs *Arguments) {

612

616 Arguments->MI->getParent()->instr_end();

617

618 if (NextMII == E)

619 return false;

620

623

626

628 return false;

629

631 return false;

632

634 return false;

635

638

640 return false;

641

642 bool ConsecutiveForward;

644 ConsecutiveForward = true;

646 ConsecutiveForward = false;

647 } else

648 return false;

649

650 NextMII = std::next(NextMII);

651 return ReplaceInstruction(MI1, Entry, MI2, ConsecutiveForward);

652}

653

654bool MicroMipsSizeReduce::ReduceXORtoXOR16(ReduceEntryFunArgs *Arguments) {

655

658

662 return false;

663

664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&

665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))

666 return false;

667

668 return ReplaceInstruction(MI, Entry);

669}

670

676

677

678 for (; MII != E; MII = NextMII) {

679 NextMII = std::next(MII);

681

682

683 if (MI->isBundle() || MI->isTransient())

684 continue;

685

686

687 Modified |= ReduceMI(MII, NextMII);

688 }

689

691}

692

693bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,

694 const ReduceEntry &Entry,

696 bool ConsecutiveForward) {

697

698 enum OperandTransfer OpTransfer = Entry.TransferOperands();

699

701 ++NumReduced;

702

703 if (OpTransfer == OT_OperandsAll) {

704 MI->setDesc(MipsII->get(Entry.NarrowOpc()));

706 return true;

707 } else {

712 switch (OpTransfer) {

713 case OT_Operand2:

714 MIB.add(MI->getOperand(2));

715 break;

716 case OT_Operands02: {

717 MIB.add(MI->getOperand(0));

718 MIB.add(MI->getOperand(2));

719 break;

720 }

721 case OT_OperandsXOR: {

722 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {

723 MIB.add(MI->getOperand(0));

724 MIB.add(MI->getOperand(1));

725 MIB.add(MI->getOperand(2));

726 } else {

727 MIB.add(MI->getOperand(0));

728 MIB.add(MI->getOperand(2));

729 MIB.add(MI->getOperand(1));

730 }

731 break;

732 }

733 case OT_OperandsMovep:

734 case OT_OperandsLwp:

735 case OT_OperandsSwp: {

736 if (ConsecutiveForward) {

737 MIB.add(MI->getOperand(0));

739 MIB.add(MI->getOperand(1));

740 if (OpTransfer == OT_OperandsMovep)

742 else

743 MIB.add(MI->getOperand(2));

744 } else {

746 MIB.add(MI->getOperand(0));

748 if (OpTransfer == OT_OperandsMovep)

749 MIB.add(MI->getOperand(1));

750 else

752 }

753

754 LLVM_DEBUG(dbgs() << "and converting 32-bit: " << *MI2

755 << " to: " << *MIB);

756

759 return true;

760 }

761 default:

763 }

764

765

767

770 return true;

771 }

772 return false;

773}

774

775bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {

776

778

779

780 if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||

781 Subtarget->hasMips32r6())

782 return false;

783

784 MipsII = static_cast<const MipsInstrInfo *>(Subtarget->getInstrInfo());

785

788

789 for (; I != E; ++I)

792}

793

794

796 return new MicroMipsSizeReduce();

797}

AMDGPU Lower Kernel Arguments

static bool isMMSourceRegister(const MachineOperand &MO)

static bool IsMovepDestinationReg(unsigned Reg)

static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp, const ReduceEntry &Entry)

static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry)

static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1)

#define MICROMIPS_SIZE_REDUCE_NAME

static bool InRange(int64_t Value, unsigned short Shift, int LBound, int HBound)

static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm)

static bool IsMovepSrcRegister(unsigned Reg)

static bool AddiuspImmValue(int64_t Value)

static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2)

static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2)

static bool isMMThreeBitGPRegister(const MachineOperand &MO)

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

SI Pre allocate WWM Registers

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

This class represents an Operation in the Expression.

FunctionPass class - This class is used to implement most global optimizations.

Describe properties that are true of each instruction in the target description file.

instr_iterator instr_begin()

instr_iterator erase_instr(MachineInstr *I)

Remove an instruction from the instruction list and delete it.

Instructions::iterator instr_iterator

instr_iterator instr_end()

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & setMIFlags(unsigned Flags) const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Wrapper class representing virtual and physical registers.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

bool operator<(int64_t V1, const APSInt &V2)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionPass * createMicroMipsSizeReducePass()

Returns an instance of the MicroMips size reduction pass.