LLVM: lib/Target/Mips/Mips16InstrInfo.cpp Source File (original) (raw)
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27#include
28#include
29#include
30#include
31#include
32#include
33#include
34
35using namespace llvm;
36
37#define DEBUG_TYPE "mips16-instrinfo"
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46
48 int &FrameIndex) const {
49 return 0;
50}
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58 int &FrameIndex) const {
59 return 0;
60}
61
65 Register SrcReg, bool KillSrc,
66 bool RenamableDest, bool RenamableSrc) const {
67 unsigned Opc = 0;
68
69 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
70 Mips::GPR32RegClass.contains(SrcReg))
71 Opc = Mips::MoveR3216;
72 else if (Mips::GPR32RegClass.contains(DestReg) &&
73 Mips::CPU16RegsRegClass.contains(SrcReg))
74 Opc = Mips::Move32R16;
75 else if ((SrcReg == Mips::HI0) &&
76 (Mips::CPU16RegsRegClass.contains(DestReg)))
77 Opc = Mips::Mfhi16, SrcReg = 0;
78 else if ((SrcReg == Mips::LO0) &&
79 (Mips::CPU16RegsRegClass.contains(DestReg)))
80 Opc = Mips::Mflo16, SrcReg = 0;
81
82 assert(Opc && "Cannot copy registers");
83
85
86 if (DestReg)
88
89 if (SrcReg)
91}
92
93std::optional
95 if (MI.isMoveReg())
97 return std::nullopt;
98}
99
102 Register SrcReg, bool isKill, int FI,
107 if (I != MBB.end()) DL = I->getDebugLoc();
109 unsigned Opc = 0;
110 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
111 Opc = Mips::SwRxSpImmX16;
112 assert(Opc && "Register class not handled!");
116}
117
125 if (I != MBB.end()) DL = I->getDebugLoc();
127 unsigned Opc = 0;
128
129 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
130 Opc = Mips::LwRxSpImmX16;
131 assert(Opc && "Register class not handled!");
134}
135
138 switch (MI.getDesc().getOpcode()) {
139 default:
140 return false;
141 case Mips::RetRA16:
142 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
143 break;
144 }
145
146 MBB.erase(MI.getIterator());
147 return true;
148}
149
150
151
153 switch (Opc) {
154 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
155 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
156 case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
157 case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
158 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
159 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
160 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
161 case Mips::Btnez16: return Mips::Bteqz16;
162 case Mips::BtnezX16: return Mips::BteqzX16;
163 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
164 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
165 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
166 case Mips::Bteqz16: return Mips::Btnez16;
167 case Mips::BteqzX16: return Mips::BtnezX16;
168 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
169 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
170 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
171 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
172 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
173 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
174 }
176}
177
180 unsigned Flags = 0) {
181 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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188 switch (Reg) {
189 case Mips::RA:
190 case Mips::S0:
191 case Mips::S1:
193 break;
194 case Mips::S2:
195 break;
196 default:
198
199 }
200 }
201}
202
203
211 bool SaveS2 = Reserved[Mips::S2];
213 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
217 if (SaveS2)
218 MIB.addReg(Mips::S2);
220 MIB.addImm(FrameSize);
221 else {
222 int Base = 2040;
223
224 int64_t Remainder = FrameSize - Base;
228 else
229 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
230 }
231}
232
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241 bool SaveS2 = Reserved[Mips::S2];
243 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
244 Mips::Restore16:Mips::RestoreX16;
245
247 unsigned Base = 2040;
248 int64_t Remainder = FrameSize - Base;
249 FrameSize = Base;
250
251
254 else
255 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
256 }
260 if (SaveS2)
262 MIB.addImm(FrameSize);
263}
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269void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
272 unsigned Reg1, unsigned Reg2) const {
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289 Mips::SP);
291}
292
293void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
297}
298
299
303 if (Amount == 0)
304 return;
305
306 if (isInt<16>(Amount))
308 else
309 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
310}
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318 unsigned &NewImm) const {
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332 int32_t lo = Imm & 0xFFFF;
333 NewImm = lo;
334 int Reg =0;
335 int SpReg = 0;
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345 RI.getAllocatableSet
346 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
347
349 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
350 !MO.getReg().isVirtual())
351 Candidates.reset(MO.getReg());
352 }
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362 int DefReg = 0;
364 if (MO.isReg() && MO.isDef()) {
365 DefReg = MO.getReg();
366 break;
367 }
368 }
369
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375
376 unsigned FirstRegSaved =0, SecondRegSaved=0;
377 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
378
380
381 if (Reg == -1) {
383 Candidates.reset(Reg);
384 if (DefReg != Reg) {
385 FirstRegSaved = Reg;
386 FirstRegSavedTo = Mips::T0;
388 }
389 }
390 else
393 NewImm = 0;
394 if (FrameReg == Mips::SP) {
396 if (SpReg == -1) {
398
399 if (DefReg!= SpReg) {
400 SecondRegSaved = SpReg;
401 SecondRegSavedTo = Mips::T1;
402 }
403 if (SecondRegSaved)
405 } else {
407 }
412 }
413 else
416 if (FirstRegSaved || SecondRegSaved) {
418 if (FirstRegSaved)
420 if (SecondRegSaved)
422 }
423 return Reg;
424}
425
426unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
427 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
428 Opc == Mips::Bimm16 ||
429 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
430 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
431 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
432 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
433 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
434 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
435 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
436 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
437 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
438 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
439}
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443 unsigned Opc) const {
445}
446
449 return get(Mips::AddiuSpImm16);
450 else
451 return get(Mips::AddiuSpImmX16);
452}
453
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465 int64_t Amount) {
466 switch (Opcode) {
467 case Mips::LbRxRyOffMemX16:
468 case Mips::LbuRxRyOffMemX16:
469 case Mips::LhRxRyOffMemX16:
470 case Mips::LhuRxRyOffMemX16:
471 case Mips::SbRxRyOffMemX16:
472 case Mips::ShRxRyOffMemX16:
473 case Mips::LwRxRyOffMemX16:
474 case Mips::SwRxRyOffMemX16:
475 case Mips::SwRxSpImmX16:
476 case Mips::LwRxSpImmX16:
478 case Mips::AddiuRxRyOffMemX16:
479 if ((Reg == Mips::PC) || (Reg == Mips::SP))
482 }
484}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
@ Available
We know the block is fully available. This is a fixpoint.
static void addSaveRestoreRegs(MachineInstrBuilder &MIB, ArrayRef< CalleeSavedInfo > CSI, unsigned Flags=0)
Definition Mips16InstrInfo.cpp:178
uint64_t IntrinsicInst * II
This file declares the machine register scavenger class.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Describe properties that are true of each instruction in the target description file.
MachineInstrBundleIterator< MachineInstr > iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
Definition Mips16InstrInfo.cpp:47
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition Mips16InstrInfo.cpp:136
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
Definition Mips16InstrInfo.cpp:464
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
Definition Mips16InstrInfo.cpp:447
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Definition Mips16InstrInfo.cpp:204
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
Definition Mips16InstrInfo.cpp:455
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Definition Mips16InstrInfo.cpp:118
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
Definition Mips16InstrInfo.cpp:152
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition Mips16InstrInfo.cpp:94
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition Mips16InstrInfo.cpp:57
static bool validSpImm8(int offset)
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Definition Mips16InstrInfo.cpp:234
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
Definition Mips16InstrInfo.cpp:62
Mips16InstrInfo(const MipsSubtarget &STI)
Definition Mips16InstrInfo.cpp:39
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
Definition Mips16InstrInfo.cpp:314
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
Definition Mips16InstrInfo.cpp:300
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Definition Mips16InstrInfo.cpp:100
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI, unsigned UncondBrOpc)
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void backward()
Update internal register state and move MBB iterator backwards.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Wrapper class representing virtual and physical registers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Define
Register definition.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
unsigned getKillRegState(bool B)
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
Definition Mips16InstrInfo.cpp:460