MipsSubtarget.cpp Source File (original) (raw)

28using namespace llvm;

32 cl::desc("MIPS Specific: Compact branch policy."),

34 "Do not use compact branches if possible."),

36 "Use compact branches where appropriate (default)."),

38 "Always use compact branches if possible.")));

40#define DEBUG_TYPE "mips-subtarget"

42#define GET_SUBTARGETINFO_TARGET_DESC

43#define GET_SUBTARGETINFO_CTOR

44#include "MipsGenSubtargetInfo.inc"

50 cl::desc("Allow for a mixture of Mips16 "

51 "and Mips32 code in a single output file"),

55 cl::desc("Compile all functions that don't use "

56 "floating point as Mips 16"),

60 cl::desc("Enable mips16 hard float."),

65 cl::desc("Enable mips16 constant islands."),

70 cl::desc("Enable gp-relative addressing of mips small data items"));

72bool MipsSubtarget::DspWarningPrinted = false;

73bool MipsSubtarget::MSAWarningPrinted = false;

74bool MipsSubtarget::VirtWarningPrinted = false;

75bool MipsSubtarget::CRCWarningPrinted = false;

76bool MipsSubtarget::GINVWarningPrinted = false;

77bool MipsSubtarget::MIPS1WarningPrinted = false;

79void MipsSubtarget::anchor() {}

85 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),

87 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),

89 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),

90 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),

91 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),

96 UseIndirectJumpsHazard(false), StrictAlign(false),

98 StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),

99 InstrInfo(

103

104 if (MipsArchVersion == MipsDefault)

105 MipsArchVersion = Mips32;

106

107

108 if (MipsArchVersion == Mips1 && !MIPS1WarningPrinted) {

109 errs() << "warning: MIPS-I support is experimental\n";

110 MIPS1WarningPrinted = true;

111 }

112

113

114

115 if (MipsArchVersion == Mips5)

116 report_fatal_error("Code generation for MIPS-V is not implemented", false);

117

118

120 "Invalid Arch & ABI pair.");

121

123 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "

124 "See -mattr=+fp64.",

125 false);

126

129 "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "

130 "Use -mcpu=mips32r2 or greater.", false);

131

133 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);

134

136 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);

137

140

141 if ( $isABI\_O32$ () && InMicroMipsMode)

143

144 if (UseIndirectJumpsHazard) {

145 if (InMicroMipsMode)

147 "cannot combine indirect jumps with hazard barriers and microMIPS");

150 "indirect jumps with hazard barriers requires MIPS32R2 or later");

151 }

153 report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given "

154 "architecture.",

155 false);

156 }

157

160

165 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);

166 }

167

168 if (NoABICalls && TM.isPositionIndependent())

169 report_fatal_error("position-independent code requires '-mabicalls'");

170

172 NoABICalls = true;

173

174

175 UseSmallSection = GPOpt;

176 if (!NoABICalls && GPOpt) {

177 errs() << "warning: cannot use small-data accesses for '-mabicalls'"

178 << "\n";

179 UseSmallSection = false;

180 }

181

182 if (hasDSPR2() && !DspWarningPrinted) {

184 errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "

185 << "greater\n";

186 DspWarningPrinted = true;

188 errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "

189 << "greater\n";

190 DspWarningPrinted = true;

191 }

192 } else if (hasDSP() && !DspWarningPrinted) {

194 errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "

195 << "greater\n";

196 DspWarningPrinted = true;

198 errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "

199 << "greater\n";

200 DspWarningPrinted = true;

201 }

202 }

203

205

207 errs() << "warning: the 'msa' ASE requires " << ArchName

208 << " revision 5 or greater\n";

209 MSAWarningPrinted = true;

210 }

212 errs() << "warning: the 'virt' ASE requires " << ArchName

213 << " revision 5 or greater\n";

214 VirtWarningPrinted = true;

215 }

217 errs() << "warning: the 'crc' ASE requires " << ArchName

218 << " revision 6 or greater\n";

219 CRCWarningPrinted = true;

220 }

222 errs() << "warning: the 'ginv' ASE requires " << ArchName

223 << " revision 6 or greater\n";

224 GINVWarningPrinted = true;

225 }

226

227 TSInfo = std::make_unique();

228

231

235}

236

238

240 return TM.isPositionIndependent();

241}

242

243

245

247 CriticalPathRCs.clear();

248 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass

249 : &Mips::GPR32RegClass);

250}

251

255

260

261

263

264 InstrItins = getInstrItineraryForCPU(CPUName);

265

266 if (InMips16Mode && !IsSoftFloat)

267 InMips16HardFloat = true;

268

269 if (StackAlignOverride)

270 stackAlignment = *StackAlignOverride;

272 stackAlignment = Align(16);

273 else {

274 assert(isABI_O32() && "Unknown ABI for stack alignment!");

275 stackAlignment = Align(8);

276 }

277

280 "support it!");

281

282 return *this;

283}

284

290

292 return TM.getRelocationModel();

293}

294

299

301 return TSInfo.get();

302}

303

307

311

315

319

320

322 RTLIB::impl___mips16_adddf3, RTLIB::impl___mips16_addsf3,

323 RTLIB::impl___mips16_divdf3, RTLIB::impl___mips16_divsf3,

324 RTLIB::impl___mips16_eqdf2, RTLIB::impl___mips16_eqsf2,

325 RTLIB::impl___mips16_extendsfdf2, RTLIB::impl___mips16_fix_truncdfsi,

326 RTLIB::impl___mips16_fix_truncsfsi, RTLIB::impl___mips16_floatsidf,

327 RTLIB::impl___mips16_floatsisf, RTLIB::impl___mips16_floatunsidf,

328 RTLIB::impl___mips16_floatunsisf, RTLIB::impl___mips16_gedf2,

329 RTLIB::impl___mips16_gesf2, RTLIB::impl___mips16_gtdf2,

330 RTLIB::impl___mips16_gtsf2, RTLIB::impl___mips16_ledf2,

331 RTLIB::impl___mips16_lesf2, RTLIB::impl___mips16_ltdf2,

332 RTLIB::impl___mips16_ltsf2, RTLIB::impl___mips16_muldf3,

333 RTLIB::impl___mips16_mulsf3, RTLIB::impl___mips16_nedf2,

334 RTLIB::impl___mips16_nesf2, RTLIB::impl___mips16_ret_dc,

335 RTLIB::impl___mips16_ret_df, RTLIB::impl___mips16_ret_sc,

336 RTLIB::impl___mips16_ret_sf, RTLIB::impl___mips16_subdf3,

337 RTLIB::impl___mips16_subsf3, RTLIB::impl___mips16_truncdfsf2,

338 RTLIB::impl___mips16_unorddf2, RTLIB::impl___mips16_unordsf2};

339

344 "Array not sorted!");

345 RTLIB::Libcall LC =

348 }

349 }

350}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file contains the simple types necessary to represent the attributes associated with functions a...

#define clEnumValN(ENUMVAL, FLAGNAME, DESC)

This file describes how to lower LLVM calls to machine code calls.

cl::opt< CompactBranchPolicy > MipsCompactBranchPolicy

This file declares the targeting of the Machinelegalizer class for Mips.

This file declares the targeting of the RegisterBankInfo class for Mips.

static cl::opt< bool > Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden, cl::desc("Enable mips16 constant islands."), cl::init(true))

static cl::opt< bool > Mixed16_32("mips-mixed-16-32", cl::init(false), cl::desc("Allow for a mixture of Mips16 " "and Mips32 code in a single output file"), cl::Hidden)

static cl::opt< bool > Mips16HardFloat("mips16-hard-float", cl::NotHidden, cl::desc("Enable mips16 hard float."), cl::init(false))

static cl::opt< bool > Mips_Os16("mips-os16", cl::init(false), cl::desc("Compile all functions that don't use " "floating point as Mips 16"), cl::Hidden)

cl::opt< CompactBranchPolicy > MipsCompactBranchPolicy("mips-compact-branches", cl::Optional, cl::init(CB_Optimal), cl::desc("MIPS Specific: Compact branch policy."), cl::values(clEnumValN(CB_Never, "never", "Do not use compact branches if possible."), clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropriate (default)."), clEnumValN(CB_Always, "always", "Always use compact branches if possible.")))

static cl::opt< bool > GPOpt("mgpopt", cl::Hidden, cl::desc("Enable gp-relative addressing of mips small data items"))

Tracks which library functions to use for a particular subtarget.

This class provides legalization strategies.

This class provides the information for the target register banks.

void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override

Definition MipsSubtarget.cpp:340

const LegalizerInfo * getLegalizerInfo() const override

Definition MipsSubtarget.cpp:308

static bool useConstantIslands()

Definition MipsSubtarget.cpp:285

bool enablePostRAScheduler() const override

This overrides the PostRAScheduler bit in the SchedModel for each CPU.

Definition MipsSubtarget.cpp:244

std::unique_ptr< InstructionSelector > InstSelector

bool useSoftFloat() const

bool isABI_N64() const

Definition MipsSubtarget.cpp:295

MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)

Definition MipsSubtarget.cpp:257

const CallLowering * getCallLowering() const override

Definition MipsSubtarget.cpp:304

std::unique_ptr< RegisterBankInfo > RegBankInfo

bool inMips16Mode() const

~MipsSubtarget() override

bool inAbs2008Mode() const

std::unique_ptr< CallLowering > CallLoweringInfo

const MipsRegisterInfo * getRegisterInfo() const override

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

const RegisterBankInfo * getRegBankInfo() const override

Definition MipsSubtarget.cpp:312

static const RTLIB::LibcallImpl HardFloatLibCalls[34]

bool isPositionIndependent() const

Definition MipsSubtarget.cpp:239

InstructionSelector * getInstructionSelector() const override

Definition MipsSubtarget.cpp:316

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

Definition MipsSubtarget.cpp:300

std::unique_ptr< LegalizerInfo > Legalizer

bool isABI_O32() const

Definition MipsSubtarget.cpp:297

bool isABI_N32() const

Definition MipsSubtarget.cpp:296

const MipsTargetLowering * getTargetLowering() const override

void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override

Definition MipsSubtarget.cpp:246

MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride)

This constructor initializes the data members to match that of the specified triple.

Definition MipsSubtarget.cpp:81

Reloc::Model getRelocationModel() const

Definition MipsSubtarget.cpp:291

CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override

Definition MipsSubtarget.cpp:252

const MipsABIInfo & getABI() const

Definition MipsSubtarget.cpp:298

Holds all the information related to register banks.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

Primary interface to the complete machine description for the target machine.

Triple - Helper class for working with autoconf configuration names.

StringRef selectMipsCPU(const Triple &TT, StringRef CPU)

Select the Mips CPU for the given triple and cpu name.

ValuesClass values(OptsTy... Options)

Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

InstructionSelector * createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &, const MipsRegisterBankInfo &)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

CodeGenOptLevel

Code generation optimization level.

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

@ CB_Never

The policy 'never' may in some circumstances or for some ISAs not be absolutely adhered to.

@ CB_Always

'always' may in some circumstances may not be absolutely adhered to, there may not be a corresponding...

@ CB_Optimal

Optimal is the default and will produce compact branches when appropriate.

LLVM_ABI void reportFatalUsageError(Error Err)

Report a fatal error that does not indicate a bug in LLVM.

This struct is a compact representation of a valid (non-zero power of two) alignment.

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.

static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl)

Return the libcall provided by Impl.