PPCMCCodeEmitter.cpp Source File (original) (raw)

27#include

28#include

30using namespace llvm;

32#define DEBUG_TYPE "mccodeemitter"

34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");

43 bool PCRel = false;

44 switch (Kind) {

50 PCRel = true;

51 }

53}

59 const MCOperand &MO = MI.getOperand(OpNo);

68 return 0;

69}

74 unsigned Opcode = MI.getOpcode();

75 if (!MCII.get(Opcode).isCall())

76 return false;

78 switch (Opcode) {

79 default:

80#ifndef NDEBUG

82#endif

83 return false;

84 case PPC::BL8_NOTOC:

85 case PPC::BL8_NOTOC_TLS:

86 case PPC::BL8_NOTOC_RM:

87 return true;

88#ifndef NDEBUG

89 case PPC::BL8:

90 case PPC::BL:

91 case PPC::BL8_TLS:

92 case PPC::BL_TLS:

93 case PPC::BLA8:

94 case PPC::BLA:

95 case PPC::BCCL:

96 case PPC::BCCLA:

97 case PPC::BCL:

98 case PPC::BCLn:

99 case PPC::BL8_NOP:

100 case PPC::BL_NOP:

101 case PPC::BL8_NOP_TLS:

102 case PPC::BLA8_NOP:

103 case PPC::BCTRL8:

104 case PPC::BCTRL:

105 case PPC::BCCCTRL8:

106 case PPC::BCCCTRL:

107 case PPC::BCCTRL8:

108 case PPC::BCCTRL:

109 case PPC::BCCTRL8n:

110 case PPC::BCCTRLn:

111 case PPC::BL8_RM:

112 case PPC::BLA8_RM:

113 case PPC::BL8_NOP_RM:

114 case PPC::BLA8_NOP_RM:

115 case PPC::BCTRL8_RM:

116 case PPC::BCTRL8_LDinto_toc:

117 case PPC::BCTRL8_LDinto_toc_RM:

118 case PPC::BL8_TLS_:

119 case PPC::TCRETURNdi8:

120 case PPC::TCRETURNai8:

121 case PPC::TCRETURNri8:

122 case PPC::TAILBCTR8:

123 case PPC::TAILB8:

124 case PPC::TAILBA8:

125 case PPC::BCLalways:

126 case PPC::BLRL:

127 case PPC::BCCLRL:

128 case PPC::BCLRL:

129 case PPC::BCLRLn:

130 case PPC::BDZL:

131 case PPC::BDNZL:

132 case PPC::BDZLA:

133 case PPC::BDNZLA:

134 case PPC::BDZLp:

135 case PPC::BDNZLp:

136 case PPC::BDZLAp:

137 case PPC::BDNZLAp:

138 case PPC::BDZLm:

139 case PPC::BDNZLm:

140 case PPC::BDZLAm:

141 case PPC::BDNZLAm:

142 case PPC::BDZLRL:

143 case PPC::BDNZLRL:

144 case PPC::BDZLRLp:

145 case PPC::BDNZLRLp:

146 case PPC::BDZLRLm:

147 case PPC::BDNZLRLm:

148 case PPC::BL_RM:

149 case PPC::BLA_RM:

150 case PPC::BL_NOP_RM:

151 case PPC::BCTRL_RM:

152 case PPC::TCRETURNdi:

153 case PPC::TCRETURNai:

154 case PPC::TCRETURNri:

155 case PPC::BCTRL_LWZinto_toc:

156 case PPC::BCTRL_LWZinto_toc_RM:

157 case PPC::TAILBCTR:

158 case PPC::TAILB:

159 case PPC::TAILBA:

160 return false;

161#endif

162 }

163}

164

168 const MCOperand &MO = MI.getOperand(OpNo);

170

171

173 return 0;

174}

175

180 const MCOperand &MO = MI.getOperand(OpNo);

182

183

185 return 0;

186}

187

192 const MCOperand &MO = MI.getOperand(OpNo);

194

195

197 return 0;

198}

199

200unsigned

204 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");

206 << 1;

207 return RegBits;

208}

209

210template

214 const MCOperand &MO = MI.getOperand(OpNo);

215 assert(!MO.isReg() && "Not expecting a register for this operand.");

218

221 Offset = IsLittleEndian ? 0 : 2;

222

223

225 return 0;

226}

227

231 const MCOperand &MO = MI.getOperand(OpNo);

234

235

237 return 0;

238}

239

240unsigned

244 const MCOperand &MO = MI.getOperand(OpNo);

247

248

251 return 0;

252}

253

254unsigned

258 const MCOperand &MO = MI.getOperand(OpNo);

259 if (MO.isImm()) {

261 "Expecting an immediate that is a multiple of 16");

263 }

264

265

268 return 0;

269}

270

271unsigned

275

276

277 const MCOperand &MO = MI.getOperand(OpNo);

278

279 assert(MO.isImm() && "Expecting an immediate operand.");

280 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");

281

282 unsigned DX = (MO.getImm() >> 3) & 0x3F;

283 return DX;

284}

285

290

291

292

293

294

295

296

297

298

299

300 const MCOperand &MO = MI.getOperand(OpNo);

303

304

305

306

308 switch (Expr->getKind()) {

309 default:

310 llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");

312

314 (void)SRE;

315

319 "specifier must be S_PCREL, S_GOT_PCREL, S_GOT_TLSGD_PCREL, "

320 "S_GOT_TLSLD_PCREL, or S_GOT_TPREL_PCREL");

321

323

324

325 return 0;

326 }

328

331 "Binary expression opcode must be an add.");

332

335

336

339

342 llvm_unreachable("Expecting to have one constant and one relocation.");

343

345 (void)SRE;

347 "Value must fit in 34 bits.");

348

349

352 "VariantKind must be VK_PCREL or VK_GOT_PCREL");

353

355

356

357 return 0;

358 }

359 }

360}

361

366

367 const MCOperand &MO = MI.getOperand(OpNo);

369}

370

371unsigned

375

376 const MCOperand &MO = MI.getOperand(OpNo);

379}

380

381unsigned

385

386 const MCOperand &MO = MI.getOperand(OpNo);

389}

390

391unsigned

395

396 const MCOperand &MO = MI.getOperand(OpNo);

399}

400

404 const MCOperand &MO = MI.getOperand(OpNo);

406

407

408

409

410

416 bool isPPC64 = TT.isPPC64();

417 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);

418}

419

423

424

425

426 const MCOperand &MO = MI.getOperand(OpNo+1);

429}

430

435 const MCOperand &MO = MI.getOperand(OpNo);

436 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||

437 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&

438 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));

439 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());

440}

441

442

443

444

445

447 for (unsigned i = 0; i < MI.getNumOperands(); i++) {

449 if (&Op == &MO)

450 return i;

451 }

452 llvm_unreachable("This operand is not part of this instruction");

453 return ~0U;

454}

455

460 if (MO.isReg()) {

461

462

463 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&

464 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||

465 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);

469 return CTX.getRegisterInfo()->getEncodingValue(Reg);

470 }

471

473 "Relocation required in an instruction that we cannot encode!");

475}

476

482

483

487 switch (Size) {

488 case 0:

489 break;

490 case 4:

492 break;

493 case 8:

494

495

498 break;

499 default:

501 }

502

503 ++MCNumEmitted;

504}

505

506

508 unsigned Opcode = MI.getOpcode();

510 return Desc.getSize();

511}

512

516

517#include "PPCGenMCCodeEmitter.inc"

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO)

Definition PPCMCCodeEmitter.cpp:446

PowerPC TLS Dynamic Call Fixup

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

Binary assembler expressions.

const MCExpr * getLHS() const

Get the left-hand side expression of the binary operator.

const MCExpr * getRHS() const

Get the right-hand side expression of the binary operator.

Opcode getOpcode() const

Get the kind of this binary expression.

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

@ Constant

Constant expressions.

@ SymbolRef

References to labels and assigned expressions.

@ Binary

Binary expressions.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

Interface to description of machine instruction set.

Instances of this class represent operands of the MCInst class.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

Wrapper class representing physical registers. Should be passed by value.

Generic base class for all target subtargets.

const Triple & getTargetTriple() const

Represent a reference to a symbol from inside an expression.

uint16_t getSpecifier() const

unsigned getDispSPE2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:392

unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:177

unsigned getDispRIHashEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:272

uint64_t getDispRI34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:363

unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:56

unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:241

unsigned getDispSPE8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:372

void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override

Encode the given Inst to bytes and append to CB.

Definition PPCMCCodeEmitter.cpp:477

unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:401

bool isNoTOCCallInstr(const MCInst &MI) const

Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.

Definition PPCMCCodeEmitter.cpp:73

unsigned getDispRIX16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:255

uint64_t getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:287

bool isPrefixedInstruction(const MCInst &MI) const

Definition PPCMCCodeEmitter.cpp:513

unsigned getDispSPE4Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:382

unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:189

unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:228

uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

getMachineOpValue - Return binary encoding of operand.

Definition PPCMCCodeEmitter.cpp:457

unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:201

uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

uint64_t getImmEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:211

unsigned getInstSizeInBytes(const MCInst &MI) const

Definition PPCMCCodeEmitter.cpp:507

unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:165

unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:420

unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const

Definition PPCMCCodeEmitter.cpp:432

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Triple - Helper class for working with autoconf configuration names.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ Prefixed

This instruction is prefixed.

MCRegister getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg, unsigned OpNo)

getRegNumForOperand - some operands use different numbering schemes for the same registers.

@ fixup_ppc_brcond14abs

14-bit absolute relocation for conditional branches.

@ fixup_ppc_half16

A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.

@ fixup_ppc_brcond14

14-bit PC relative relocation for conditional branches.

@ fixup_ppc_half16dq

A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.

@ fixup_ppc_half16ds

A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.

@ fixup_ppc_nofixup

Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...

@ fixup_ppc_br24abs

24-bit absolute relocation for direct branches like 'ba' and 'bla'.

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)

DWARFExpression::Operation Op

MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Definition PPCMCCodeEmitter.cpp:36

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

static uint16_t getSpecifier(const MCSymbolRefExpr *SRE)

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.