PPCMachineScheduler.cpp Source File (original) (raw)

12using namespace llvm;

16 cl::desc("Disable scheduling addi instruction before"

20 cl::desc("Enable scheduling addi instruction as early"

21 "as possible post ra"),

29bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,

30 SchedCandidate &TryCand,

33 return false;

37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {

38 TryCand.Reason = Stall;

39 return true;

40 }

41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {

42 TryCand.Reason = NoCand;

43 return true;

44 }

46 return false;

47}

57 return true;

58 }

66 if (DAG->isTrackingPressure() &&

72 if (DAG->isTrackingPressure() &&

82 bool SameBoundary = Zone != nullptr;

83 if (SameBoundary) {

87 if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() &&

95 }

100

101

102

105 bool CandIsClusterSucc =

107 bool TryCandIsClusterSucc =

109

110 if (tryGreater(TryCandIsClusterSucc, CandIsClusterSucc, TryCand, Cand,

113

114 if (SameBoundary) {

115

119 }

120

121

122 if (DAG->isTrackingPressure() &&

126

127 if (SameBoundary) {

128

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141 Rem .IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, *Zone))

143

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148 }

149 }

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156 return true;

157

158

159

160 if (SameBoundary) {

161 if (biasAddiLoadCandidate(Cand, TryCand, *Zone))

163 }

164

166}

167

171 return false;

172

175 return true;

176 }

177 return false;

178}

179

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184

187 return true;

188 }

189

190

191 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),

192 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))

194

195

198 bool CandIsClusterSucc =

200 bool TryCandIsClusterSucc =

202

203 if (tryGreater(TryCandIsClusterSucc, CandIsClusterSucc, TryCand, Cand,

206

207

215

216

219 }

220

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230 return true;

231

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238

240}

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static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand)

Definition PPCMachineScheduler.cpp:24

static cl::opt< bool > EnableAddiHeuristic("ppc-postra-bias-addi", cl::desc("Enable scheduling addi instruction as early" "as possible post ra"), cl::Hidden, cl::init(true))

static cl::opt< bool > DisableAddiLoadHeuristic("disable-ppc-sched-addi-load", cl::desc("Disable scheduling addi instruction before" "load for ppc"), cl::Hidden)

MachineSchedPolicy RegionPolicy

const TargetSchedModel * SchedModel

const TargetRegisterInfo * TRI

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

virtual void leaveMBB()

Tell the strategy that current MBB is done.

virtual void enterMBB(MachineBasicBlock *MBB)

Tell the strategy that MBB is about to be processed.

SUnit * pickNode(bool &IsTopNode) override

Pick the next node to schedule.

Definition PPCMachineScheduler.cpp:257

void enterMBB(MachineBasicBlock *MBB) override

Tell the strategy that MBB is about to be processed.

Definition PPCMachineScheduler.cpp:242

bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override

Apply a set of heuristics to a new candidate for PostRA scheduling.

Definition PPCMachineScheduler.cpp:180

bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const

Definition PPCMachineScheduler.cpp:168

void leaveMBB() override

Tell the strategy that current MBB is done.

Definition PPCMachineScheduler.cpp:247

void initialize(ScheduleDAGMI *Dag) override

Initialize the strategy after building the DAG for a new region.

Definition PPCMachineScheduler.cpp:252

bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const override

Apply a set of heuristics to a new candidate.

Definition PPCMachineScheduler.cpp:49

void initialize(ScheduleDAGMI *Dag) override

Initialize the strategy after building the DAG for a new region.

SUnit * pickNode(bool &IsTopNode) override

Pick the next node to schedule.

Scheduling unit. This is a node in the scheduling DAG.

unsigned NodeNum

Entry # of node in the node vector.

unsigned ParentClusterIdx

The parent cluster id.

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

Each Scheduling boundary is associated with ready queues.

LLVM_ABI unsigned getLatencyStallCycles(SUnit *SU)

Get the difference between the given SUnit's ready time and the current cycle.

unsigned getCurrMOps() const

Micro-ops issued in the current cycle.

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI unsigned getWeakLeft(const SUnit *SU, bool isTop)

LLVM_ABI bool tryPressure(const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)

LLVM_ABI bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)

bool isTheSameCluster(unsigned A, unsigned B)

Return whether the input cluster ID's are the same and valid.

LLVM_ABI bool tryGreater(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)

LLVM_ABI bool tryLess(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)

Return true if this heuristic determines order.

LLVM_ABI int biasPhysReg(const SUnit *SU, bool isTop)

Minimize physical register live ranges.

Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...

LLVM_ABI void initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel)

SchedResourceDelta ResDelta

unsigned DemandedResources

PressureChange CriticalMax

PressureChange CurrentMax