LLVM: lib/Target/Hexagon/RDFCopy.cpp Source File (original) (raw)

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27#include

28#include

29

30using namespace llvm;

31using namespace rdf;

32

33#ifndef NDEBUG

36#endif

37

39 unsigned Opc = MI->getOpcode();

40 switch (Opc) {

41 case TargetOpcode::COPY: {

44 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());

45 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());

49 if (TRI.getMinimalPhysRegClass(DstR.asMCReg()) !=

50 TRI.getMinimalPhysRegClass(SrcR.asMCReg()))

51 return false;

52 if (!DFG.isTracked(SrcR) || !DFG.isTracked(DstR))

53 return false;

54 EM.insert(std::make_pair(DstR, SrcR));

55 return true;

56 }

57 case TargetOpcode::REG_SEQUENCE:

59 }

60 return false;

61}

62

63void CopyPropagation::recordCopy(NodeAddr<StmtNode*> SA, EqualityMap &EM) {

64 CopyMap.insert(std::make_pair(SA.Id, EM));

66

67 for (auto I : EM) {

68 auto FS = DefM.find(I.second.Id);

69 if (FS == DefM.end() || FS->second.empty())

70 continue;

71 RDefMap[I.second][SA.Id] = FS->second.top()->Id;

72

73 RDefMap[I.first];

74 }

75}

76

77

79 RegisterSet RRs(DFG.getPRI());

81 RRs.insert(RA.Addr->getRegRef(DFG));

82 bool Common = false;

83 for (auto &R : RDefMap) {

84 if (!RRs.count(R.first))

85 continue;

86 Common = true;

87 break;

88 }

89 if (!Common)

90 return;

91

92 for (auto &R : RDefMap) {

93 if (!RRs.count(R.first))

94 continue;

95 auto F = DefM.find(R.first.Id);

96 if (F == DefM.end() || F->second.empty())

97 continue;

98 R.second[IA.Id] = F->second.top()->Id;

99 }

100}

101

102bool CopyPropagation::scanBlock(MachineBasicBlock *B) {

104 NodeAddr<BlockNode*> BA = DFG.findBlock(B);

105 DFG.markBlock(BA.Id, DefM);

106

107 for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) {

109 NodeAddr<StmtNode*> SA = IA;

110 EqualityMap EM(RegisterRefLess(DFG.getPRI()));

111 if (interpretAsCopy(SA.Addr->getCode(), EM))

112 recordCopy(SA, EM);

113 }

114

115 updateMap(IA);

116 DFG.pushAllDefs(IA, DefM);

117 }

118

120 for (auto *I : *N)

121 Changed |= scanBlock(I->getBlock());

122

123 DFG.releaseBlock(BA.Id, DefM);

125}

126

128 scanBlock(&DFG.getMF().front());

129

131 dbgs() << "Copies:\n";

132 for (NodeId I : Copies) {

134 dbgs() << " eq: {";

135 if (auto It = CopyMap.find(I); It != CopyMap.end()) {

136 for (auto J : It->second)

139 }

140 dbgs() << " }\n";

141 }

142 dbgs() << "\nRDef map:\n";

143 for (auto R : RDefMap) {

145 for (auto &M : R.second)

148 dbgs() << " }\n";

149 }

150 }

151

153#ifndef NDEBUG

154 bool HasLimit = CpLimit.getNumOccurrences() > 0;

155#endif

156

161 return RR.asMCReg();

163 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex()))

164 return S.getSubReg();

167 };

168

170

171 for (NodeId C : Copies) {

172#ifndef NDEBUG

174 break;

175#endif

177 auto FS = CopyMap.find(SA.Id);

178 if (FS == CopyMap.end())

179 continue;

180

183 RegisterRef DR = DA.Addr->getRegRef(DFG);

184 auto FR = EM.find(DR);

185 if (FR == EM.end())

186 continue;

189 continue;

190

191 auto &RDefSR = RDefMap[SR];

192 NodeId RDefSR_SA = RDefSR[SA.Id];

193

194 for (NodeId N = DA.Addr->getReachedUse(), NextN; N; N = NextN) {

195 auto UA = DFG.addr<UseNode*>(N);

197 uint16_t F = UA.Addr->getFlags();

199 continue;

200 if (!PRI.equal_to(UA.Addr->getRegRef(DFG), DR))

201 continue;

202

205 if (RDefSR[IA.Id] != RDefSR_SA)

206 continue;

207

209 if (Op.isTied())

210 continue;

215 }

216

218 Op.setReg(NewReg);

219 Op.setSubReg(0);

220 DFG.unlinkUse(UA, false);

221 if (RDefSR_SA != 0) {

222 UA.Addr->linkToDef(UA.Id, DFG.addr<DefNode*>(RDefSR_SA));

223 } else {

224 UA.Addr->setReachingDef(0);

225 UA.Addr->setSibling(0);

226 }

227

229 #ifndef NDEBUG

231 break;

233 #endif

234

235 auto FC = CopyMap.find(IA.Id);

236 if (FC != CopyMap.end()) {

237

238 auto &M = FC->second;

239 for (auto &J : M) {

240 if (!PRI.equal_to(J.second, DR))

241 continue;

242 J.second = SR;

243 break;

244 }

245 }

246 }

247 }

248 }

249

251}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Register const TargetRegisterInfo * TRI

static cl::opt< unsigned > CpLimit("rdf-cp-limit", cl::init(0), cl::Hidden)

static unsigned CpCount

Definition RDFCopy.cpp:35

SI optimize exec mask operations pre RA

Wrapper class representing physical registers. Should be passed by value.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.

bool isValid() const

Returns true if this iterator is not yet at the end.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

const LaneBitmask LaneMask

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

initializer< Ty > init(const Ty &Val)

Print(const T &, const DataFlowGraph &) -> Print< T >

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

DomTreeNodeBase< MachineBasicBlock > MachineDomTreeNode

DWARFExpression::Operation Op

std::map< RegisterRef, RegisterRef, RegisterRefLess > EqualityMap

virtual bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM)

Definition RDFCopy.cpp:38

bool run()

Definition RDFCopy.cpp:127

bool equal_to(RegisterRef A, RegisterRef B) const

NodeId getSibling() const

constexpr MCRegister asMCReg() const

MachineInstr * getCode() const