RISCVAsmBackend.cpp Source File (original) (raw)

26using namespace llvm;

33 cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"));

37 cl::desc("When generating R_RISCV_ALIGN, insert $alignment-2 "

38 "bytes of NOPs even in norvc code"));

41 bool Is64Bit, bool IsLittleEndian,

45 STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {

47}

50 if (STI.getTargetTriple().isOSBinFormatELF()) {

51 unsigned Type;

53#define ELF_RELOC(NAME, ID) .Case(#NAME, ID)

54#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"

55#undef ELF_RELOC

56#define ELF_RISCV_NONSTANDARD_RELOC(_VENDOR, NAME, ID) .Case(#NAME, ID)

57#include "llvm/BinaryFormat/ELFRelocs/RISCV_nonstandard.def"

58#undef ELF_RISCV_NONSTANDARD_RELOC

59 .Case("BFD_RELOC_NONE", ELF::R_RISCV_NONE)

60 .Case("BFD_RELOC_32", ELF::R_RISCV_32)

61 .Case("BFD_RELOC_64", ELF::R_RISCV_64)

63 if (Type != -1u)

65 }

66 return std::nullopt;

67}

75 {"fixup_riscv_hi20", 12, 20, 0},

76 {"fixup_riscv_lo12_i", 20, 12, 0},

77 {"fixup_riscv_12_i", 20, 12, 0},

78 {"fixup_riscv_lo12_s", 0, 32, 0},

79 {"fixup_riscv_pcrel_hi20", 12, 20, 0},

80 {"fixup_riscv_pcrel_lo12_i", 20, 12, 0},

81 {"fixup_riscv_pcrel_lo12_s", 0, 32, 0},

82 {"fixup_riscv_jal", 12, 20, 0},

83 {"fixup_riscv_branch", 0, 32, 0},

84 {"fixup_riscv_rvc_jump", 2, 11, 0},

85 {"fixup_riscv_rvc_branch", 0, 16, 0},

86 {"fixup_riscv_rvc_imm", 0, 16, 0},

87 {"fixup_riscv_call", 0, 64, 0},

88 {"fixup_riscv_call_plt", 0, 64, 0},

90 {"fixup_riscv_qc_e_branch", 0, 48, 0},

91 {"fixup_riscv_qc_e_32", 16, 32, 0},

92 {"fixup_riscv_qc_abs20_u", 0, 32, 0},

93 {"fixup_riscv_qc_e_call_plt", 0, 48, 0},

96 {"fixup_riscv_nds_branch_10", 0, 32, 0},

97 };

99 "Not all fixup kinds added to Infos array");

100

101

102

104 return {};

105

108

110 "Invalid kind!");

112}

113

118 bool Resolved) const {

120 auto Kind = Fixup.getKind();

121

122

123 if (!Resolved)

124 return true;

125

126 switch (Kind) {

127 default:

128 return false;

130

131

134

135

139

140

143

144

145 return Offset > 1048574 || Offset < -1048576;

147

148

149 return true;

150 }

151}

152

153

154

155

158 switch (Opcode) {

159 case RISCV::C_BEQZ:

160 return RISCV::BEQ;

161 case RISCV::C_BNEZ:

162 return RISCV::BNE;

163 case RISCV::C_J:

164 case RISCV::C_JAL:

165

166

167 return RISCV::JAL;

168 case RISCV::C_LI:

169 if (!STI.hasFeature(RISCV::FeatureVendorXqcili))

170 break;

171

172

173

174

175

176

177

178

179 return RISCV::QC_E_LI;

180 case RISCV::JAL: {

181

182 if (!STI.hasFeature(RISCV::FeatureVendorXqcilb))

183 break;

184

185

187 if (Reg == RISCV::X0)

188 return RISCV::QC_E_J;

189 if (Reg == RISCV::X1)

190 return RISCV::QC_E_JAL;

191

192 break;

193 }

194 case RISCV::BEQ:

195 return RISCV::PseudoLongBEQ;

196 case RISCV::BNE:

197 return RISCV::PseudoLongBNE;

198 case RISCV::BLT:

199 return RISCV::PseudoLongBLT;

200 case RISCV::BGE:

201 return RISCV::PseudoLongBGE;

202 case RISCV::BLTU:

203 return RISCV::PseudoLongBLTU;

204 case RISCV::BGEU:

205 return RISCV::PseudoLongBGEU;

206 case RISCV::QC_BEQI:

207 return RISCV::PseudoLongQC_BEQI;

208 case RISCV::QC_BNEI:

209 return RISCV::PseudoLongQC_BNEI;

210 case RISCV::QC_BLTI:

211 return RISCV::PseudoLongQC_BLTI;

212 case RISCV::QC_BGEI:

213 return RISCV::PseudoLongQC_BGEI;

214 case RISCV::QC_BLTUI:

215 return RISCV::PseudoLongQC_BLTUI;

216 case RISCV::QC_BGEUI:

217 return RISCV::PseudoLongQC_BGEUI;

218 case RISCV::QC_E_BEQI:

219 return RISCV::PseudoLongQC_E_BEQI;

220 case RISCV::QC_E_BNEI:

221 return RISCV::PseudoLongQC_E_BNEI;

222 case RISCV::QC_E_BLTI:

223 return RISCV::PseudoLongQC_E_BLTI;

224 case RISCV::QC_E_BGEI:

225 return RISCV::PseudoLongQC_E_BGEI;

226 case RISCV::QC_E_BLTUI:

227 return RISCV::PseudoLongQC_E_BLTUI;

228 case RISCV::QC_E_BGEUI:

229 return RISCV::PseudoLongQC_E_BGEUI;

230 }

231

232

233 return Opcode;

234}

235

238 if (STI.hasFeature(RISCV::FeatureExactAssembly))

239 return;

240

243 default:

245 case RISCV::C_BEQZ:

246 case RISCV::C_BNEZ:

247 case RISCV::C_J:

248 case RISCV::C_JAL: {

250 assert(Success && "Can't uncompress instruction");

253 "Branch Relaxation Error");

254 break;

255 }

256 case RISCV::JAL: {

257

258

259 assert(STI.hasFeature(RISCV::FeatureVendorXqcilb) &&

260 "JAL is only relaxable with Xqcilb");

263 "JAL only relaxable with rd=x0 or rd=x1");

266 break;

267 }

268 case RISCV::C_LI: {

269

270

271

272

273

274

275

276

277

278 assert(STI.hasFeature(RISCV::FeatureVendorXqcili) &&

279 "C.LI is only relaxable with Xqcili");

283 break;

284 }

285 case RISCV::BEQ:

286 case RISCV::BNE:

287 case RISCV::BLT:

288 case RISCV::BGE:

289 case RISCV::BLTU:

290 case RISCV::BGEU:

291 case RISCV::QC_BEQI:

292 case RISCV::QC_BNEI:

293 case RISCV::QC_BLTI:

294 case RISCV::QC_BGEI:

295 case RISCV::QC_BLTUI:

296 case RISCV::QC_BGEUI:

297 case RISCV::QC_E_BEQI:

298 case RISCV::QC_E_BNEI:

299 case RISCV::QC_E_BLTI:

300 case RISCV::QC_E_BGEI:

301 case RISCV::QC_E_BLTUI:

302 case RISCV::QC_E_BGEUI:

307 break;

308 }

309 Inst = std::move(Res);

310}

311

312

313

314

316

317

318

319

320

321

322

323 auto *Sec = F.getParent();

324 if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable())

325 return false;

326

327

329 unsigned MinNopLen =

330 AlignRvc || STI->hasFeature(RISCV::FeatureStdExtZca) ? 2 : 4;

331 if (F.getAlignment() <= MinNopLen)

332 return false;

333

334 Size = F.getAlignment().value() - MinNopLen;

338 F.setVarFixups({Fixup});

339 F.setLinkerRelaxable();

340 return true;

341}

342

344 int64_t LineDelta = F.getDwarfLineDelta();

345 const MCExpr &AddrDelta = F.getDwarfAddrDelta();

347

348

349 if (AddrDelta.evaluateAsAbsolute(Value, *Asm))

350 return false;

351 [[maybe_unused]] bool IsAbsolute =

353 assert(IsAbsolute && "CFA with invalid expression");

354

357

358

360 OS << uint8_t(dwarf::DW_LNS_advance_line);

362 }

363

364

365

366

367 unsigned PCBytes;

368 if (Value > 60000) {

370 OS << uint8_t(dwarf::DW_LNS_extended_op) << uint8_t(PCBytes + 1)

371 << uint8_t(dwarf::DW_LNE_set_address);

373 } else {

374 PCBytes = 2;

375 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);

377 }

379

381 OS << uint8_t(dwarf::DW_LNS_extended_op);

383 OS << uint8_t(dwarf::DW_LNE_end_sequence);

384 } else {

385 OS << uint8_t(dwarf::DW_LNS_copy);

386 }

387

388 F.setVarContents(Data);

391 return true;

392}

393

395 const MCExpr &AddrDelta = F.getDwarfAddrDelta();

398 if (AddrDelta.evaluateAsAbsolute(Value, *Asm))

399 return false;

400 [[maybe_unused]] bool IsAbsolute =

402 assert(IsAbsolute && "CFA with invalid expression");

403

404 assert(getContext().getAsmInfo()->getMinInstAlignment() == 1 &&

405 "expected 1-byte alignment");

406 if (Value == 0) {

407 F.clearVarContents();

408 F.clearVarFixups();

409 return true;

410 }

411

412 auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,

413 std::pair<unsigned, unsigned> Fixup) {

417 };

418

422 OS << uint8_t(dwarf::DW_CFA_advance_loc);

423 AddFixups(0, {ELF::R_RISCV_SET6, ELF::R_RISCV_SUB6});

425 OS << uint8_t(dwarf::DW_CFA_advance_loc1);

427 AddFixups(1, {ELF::R_RISCV_SET8, ELF::R_RISCV_SUB8});

429 OS << uint8_t(dwarf::DW_CFA_advance_loc2);

431 AddFixups(1, {ELF::R_RISCV_SET16, ELF::R_RISCV_SUB16});

433 OS << uint8_t(dwarf::DW_CFA_advance_loc4);

435 AddFixups(1, {ELF::R_RISCV_SET32, ELF::R_RISCV_SUB32});

436 } else {

438 }

439 F.setVarContents(Data);

440 F.setVarFixups(Fixups);

441 return true;

442}

443

445 int64_t &Value) const {

447 return std::make_pair(false, false);

451 }

453}

454

458

459

460

461 if (STI.hasFeature(RISCV::FeatureExactAssembly))

462 return false;

463

465}

466

469

470

471

472

473

474

476 OS.write("\0", 1);

478 }

479

480

481

482 if (Count % 4 == 2) {

483

484

485 OS.write("\x01\0", 2);

487 }

488

489

491 OS.write("\x13\0\0\0", 4);

492

493 return true;

494}

495

498 switch (Fixup.getKind()) {

499 default:

509 return Value & 0xfff;

512 Ctx.reportError(Fixup.getLoc(),

513 "operand must be a constant 12-bit integer");

514 }

515 return Value & 0xfff;

518 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);

521

522 return ((Value + 0x800) >> 12) & 0xfffff;

525 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

527 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");

528

529 unsigned Sbit = (Value >> 20) & 0x1;

530 unsigned Hi8 = (Value >> 12) & 0xff;

531 unsigned Mid1 = (Value >> 11) & 0x1;

532 unsigned Lo10 = (Value >> 1) & 0x3ff;

533

534

535

536

537 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;

539 }

543 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

545 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");

546

547

548 unsigned Sbit = (Value >> 12) & 0x1;

549 unsigned Hi1 = (Value >> 11) & 0x1;

550 unsigned Mid6 = (Value >> 5) & 0x3f;

551 unsigned Lo4 = (Value >> 1) & 0xf;

552

553

554

555

556 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);

558 }

561

562

563

564 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;

566 return UpperImm | ((LowerImm << 20) << 32);

567 }

570 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

571

572 unsigned Bit11 = (Value >> 11) & 0x1;

573 unsigned Bit4 = (Value >> 4) & 0x1;

574 unsigned Bit9_8 = (Value >> 8) & 0x3;

575 unsigned Bit10 = (Value >> 10) & 0x1;

576 unsigned Bit6 = (Value >> 6) & 0x1;

577 unsigned Bit7 = (Value >> 7) & 0x1;

578 unsigned Bit3_1 = (Value >> 1) & 0x7;

579 unsigned Bit5 = (Value >> 5) & 0x1;

580 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |

581 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;

583 }

586 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

587

588 unsigned Bit8 = (Value >> 8) & 0x1;

589 unsigned Bit7_6 = (Value >> 6) & 0x3;

590 unsigned Bit5 = (Value >> 5) & 0x1;

591 unsigned Bit4_3 = (Value >> 3) & 0x3;

592 unsigned Bit2_1 = (Value >> 1) & 0x3;

593 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |

594 (Bit5 << 2);

596 }

599 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

600 unsigned Bit5 = (Value >> 5) & 0x1;

601 unsigned Bit4_0 = Value & 0x1f;

602 Value = (Bit5 << 12) | (Bit4_0 << 2);

604 }

607 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

608 return Value & 0xffffffffu;

609 }

612 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

613 unsigned Bit19 = (Value >> 19) & 0x1;

614 unsigned Bit14_0 = Value & 0x7fff;

615 unsigned Bit18_15 = (Value >> 15) & 0xf;

616 Value = (Bit19 << 31) | (Bit14_0 << 16) | (Bit18_15 << 12);

618 }

621 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

623 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");

630 Value = (Bit31_16 << 32ull) | (Bit12 << 31) | (Bit10_5 << 25) |

631 (Bit15_13 << 17) | (Bit4_1 << 8) | (Bit11 << 7);

633 }

636 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");

638 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");

639

640 unsigned Sbit = (Value >> 10) & 0x1;

641 unsigned Hi5 = (Value >> 5) & 0x1f;

642 unsigned Lo4 = (Value >> 1) & 0xf;

643

644

645

646 Value = (Sbit << 31) | (Hi5 << 25) | (Lo4 << 8);

648 }

649 }

650}

651

652bool RISCVAsmBackend::isPCRelFixupResolved(const MCSymbol *SymA,

654

655

656 if (.getParent()->isLinkerRelaxable())

657 return true;

658

659

660

661

662

663 if (!PCRelTemp)

665 PCRelTemp->setFragment(const_cast<MCFragment *>(&F));

666 MCValue Res;

670}

671

672

673

674

675

676

681 return nullptr;

682

684 if (!AUIPCSymbol)

685 return nullptr;

687 if ()

688 return nullptr;

689

691 if (DF->getContents().size() == Offset) {

692 DF = DF->getNext();

693 if ()

694 return nullptr;

696 }

697

698 for (const MCFixup &F : DF->getFixups()) {

699 if (F.getOffset() != Offset)

700 continue;

701 auto Kind = F.getKind();

704 *DFOut = DF;

705 return &F;

706 }

707 break;

708 }

709 switch (Kind) {

710 case ELF::R_RISCV_GOT_HI20:

711 case ELF::R_RISCV_TLS_GOT_HI20:

712 case ELF::R_RISCV_TLS_GD_HI20:

713 case ELF::R_RISCV_TLSDESC_HI20:

714 *DFOut = DF;

715 return &F;

716 }

717 }

718

719 return nullptr;

720}

721

726 const MCFixup *AUIPCFixup;

729 switch (Fixup.getKind()) {

730 default:

731

732 return {};

735 AUIPCFixup =

737 if (!AUIPCFixup) {

739 "could not find corresponding %pcrel_hi");

740 return true;

741 }

742

743

744

747 return true;

748 break;

749 }

750 }

751

753 return false;

754

756 if (SA.isUndefined())

757 return false;

758

762 if (!IsResolved)

763 return false;

764

766 Value -= Asm->getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset();

767

769 isPCRelFixupResolved(AUIPCTarget.getAddSym(), *AUIPCDF);

770}

771

775 switch (Fixup.getKind()) {

776 default:

777

778 return;

783 VendorIdentifier = "QUALCOMM";

784 break;

786 VendorIdentifier = "ANDES";

787 break;

788 }

789

790

791

793 MCSymbol *VendorSymbol = Ctx.createLocalSymbol(VendorIdentifier);

794 auto [It, Inserted] =

795 VendorSymbols.try_emplace(VendorIdentifier, VendorSymbol);

796

797 if (Inserted) {

798

800 Asm->registerSymbol(*VendorSymbol);

801 } else {

802

803 VendorSymbol = It->getValue();

804 }

805

808

809

812 Asm->getWriter().recordRelocation(F, VendorFixup, VendorTarget, VendorValue);

813}

814

816

817

818

819

820

821 switch (Kind) {

822 default:

823 break;

828 return false;

829 }

830 return true;

831}

832

835 bool IsResolved) {

836 uint64_t FixedValueA, FixedValueB;

837 if (Target.getSubSym()) {

839 "relocatable SymA-SymB cannot have relocation specifier");

840 unsigned TA = 0, TB = 0;

841 switch (Fixup.getKind()) {

843 TA = ELF::R_RISCV_ADD8;

844 TB = ELF::R_RISCV_SUB8;

845 break;

847 TA = ELF::R_RISCV_ADD16;

848 TB = ELF::R_RISCV_SUB16;

849 break;

851 TA = ELF::R_RISCV_ADD32;

852 TB = ELF::R_RISCV_SUB32;

853 break;

855 TA = ELF::R_RISCV_ADD64;

856 TB = ELF::R_RISCV_SUB64;

857 break;

859 TA = ELF::R_RISCV_SET_ULEB128;

860 TB = ELF::R_RISCV_SUB_ULEB128;

861 break;

862 default:

864 }

869 Asm->getWriter().recordRelocation(F, FA, A, FixedValueA);

870 Asm->getWriter().recordRelocation(F, FB, B, FixedValueB);

871 FixedValue = FixedValueA - FixedValueB;

872 return false;

873 }

874

875

876

877 bool NeedsRelax = Fixup.isLinkerRelaxable() &&

879 if (NeedsRelax)

880 IsResolved = false;

881

882 if (IsResolved && Fixup.isPCRel())

883 IsResolved = isPCRelFixupResolved(Target.getAddSym(), F);

884

885 if (!IsResolved) {

886

887

889

890 Asm->getWriter().recordRelocation(F, Fixup, Target, FixedValue);

891

892 if (NeedsRelax) {

893

894

899 Asm->getWriter().recordRelocation(F, RelaxFixup, RelaxTarget, RelaxValue);

900 }

901 }

902

903 return false;

904}

905

906

907

908

910 switch (Kind) {

911 default:

912 return false;

913

918 return true;

919 }

920}

921

928 return;

932 return;

933

935

936

937 Value <<= Info.TargetOffset;

938

939 unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;

940 assert(Fixup.getOffset() + NumBytes <= F.getSize() &&

941 "Invalid fixup offset!");

942

943

944

945

947 for (unsigned i = 0; i != NumBytes; ++i) {

948 unsigned Idx = SwapValue ? (NumBytes - 1 - i) : i;

950 }

951}

952

953std::unique_ptr

957

964 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), TT.isLittleEndian(),

966}

unsigned const MachineRegisterInfo * MRI

static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file implements a class to represent arbitrary precision integral constant values and operations...

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")

static unsigned getRelaxedOpcode(unsigned Opcode)

PowerPC TLS Dynamic Call Fixup

static cl::opt< bool > AlignRvc("riscv-align-rvc", cl::init(true), cl::Hidden, cl::desc("When generating R_RISCV_ALIGN, insert $alignment-2 " "bytes of NOPs even in norvc code"))

static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind)

Definition RISCVAsmBackend.cpp:815

static bool isDataFixup(unsigned Kind)

Definition RISCVAsmBackend.cpp:909

static const MCFixup * getPCRelHiFixup(const MCSpecifierExpr &Expr, const MCFragment **DFOut)

Definition RISCVAsmBackend.cpp:677

static cl::opt< bool > ULEB128Reloc("riscv-uleb128-reloc", cl::init(true), cl::Hidden, cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate"))

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Generic interface to target specific assembler backends.

const llvm::endianness Endian

MCAsmBackend(llvm::endianness Endian)

virtual MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const

Get information on a fixup kind.

MCContext & getContext() const

unsigned getCodePointerSize() const

Get the code pointer size in bytes.

Binary assembler expressions.

const MCExpr * getLHS() const

Get the left-hand side expression of the binary operator.

const MCExpr * getRHS() const

Get the right-hand side expression of the binary operator.

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

LLVM_ABI MCSymbol * createTempSymbol()

Create a temporary symbol with a unique name.

const MCAsmInfo * getAsmInfo() const

LLVM_ABI void reportError(SMLoc L, const Twine &Msg)

Base class for the full range of assembler expressions which are needed for parsing.

LLVM_ABI bool evaluateAsRelocatable(MCValue &Res, const MCAssembler *Asm) const

Try to evaluate the expression to a relocatable value, i.e.

static LLVM_ABI bool evaluateSymbolicAdd(const MCAssembler *, bool, const MCValue &, const MCValue &, MCValue &)

LLVM_ABI bool evaluateKnownAbsolute(int64_t &Res, const MCAssembler &Asm) const

Aggressive variant of evaluateAsRelocatable when relocations are unavailable (e.g.

Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...

static MCFixupKind getDataKindForSize(unsigned Size)

Return the generic fixup kind for a value with the given size.

const MCExpr * getValue() const

uint32_t getOffset() const

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

MCFixupKind getKind() const

const MCExpr & getLEBValue() const

MCSection * getParent() const

LLVM_ABI void setVarFixups(ArrayRef< MCFixup > Fixups)

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

ArrayRef< MCOperand > getOperands() const

void addOperand(const MCOperand Op)

void setOpcode(unsigned Op)

const MCOperand & getOperand(unsigned i) const

MCRegister getReg() const

Returns the register number.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Extension point for target-specific MCExpr subclasses with a relocation specifier,...

const MCExpr * getSubExpr() const

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

void setFragment(MCFragment *F) const

Mark the symbol as defined in the fragment F.

LLVM_ABI void setVariableValue(const MCExpr *Value)

MCSection & getSection() const

Get the section associated with a defined, non-absolute symbol.

MCFragment * getFragment() const

uint64_t getOffset() const

static MCValue get(const MCSymbol *SymA, const MCSymbol *SymB=nullptr, int64_t Val=0, uint32_t Specifier=0)

const MCSymbol * getAddSym() const

int64_t getConstant() const

const MCSymbol * getSubSym() const

std::optional< bool > evaluateFixup(const MCFragment &, MCFixup &, MCValue &, uint64_t &) override

Definition RISCVAsmBackend.cpp:722

std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override

Definition RISCVAsmBackend.cpp:954

void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override

Relax the instruction in the given fragment to the next wider instruction.

Definition RISCVAsmBackend.cpp:236

bool relaxAlign(MCFragment &F, unsigned &Size) override

Definition RISCVAsmBackend.cpp:315

bool addReloc(const MCFragment &, const MCFixup &, const MCValue &, uint64_t &FixedValue, bool IsResolved)

Definition RISCVAsmBackend.cpp:833

MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override

Get information on a fixup kind.

Definition RISCVAsmBackend.cpp:69

RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, bool IsLittleEndian, const MCTargetOptions &Options)

Definition RISCVAsmBackend.cpp:40

std::pair< bool, bool > relaxLEB128(MCFragment &LF, int64_t &Value) const override

Definition RISCVAsmBackend.cpp:444

void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved) override

Definition RISCVAsmBackend.cpp:922

bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override

Write an (optimal) nop sequence of Count bytes to the given output.

Definition RISCVAsmBackend.cpp:467

void maybeAddVendorReloc(const MCFragment &, const MCFixup &)

Definition RISCVAsmBackend.cpp:772

bool mayNeedRelaxation(unsigned Opcode, ArrayRef< MCOperand > Operands, const MCSubtargetInfo &STI) const override

Check whether the given instruction (encoded as Opcode+Operands) may need relaxation.

Definition RISCVAsmBackend.cpp:455

bool fixupNeedsRelaxationAdvanced(const MCFragment &, const MCFixup &, const MCValue &, uint64_t, bool) const override

Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...

Definition RISCVAsmBackend.cpp:114

std::optional< MCFixupKind > getFixupKind(StringRef Name) const override

Map a relocation name used in .reloc to a fixup kind.

Definition RISCVAsmBackend.cpp:49

bool relaxDwarfCFA(MCFragment &) const override

Definition RISCVAsmBackend.cpp:394

bool relaxDwarfLineAddr(MCFragment &) const override

Definition RISCVAsmBackend.cpp:343

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

raw_ostream & write_zeros(unsigned NumZeros)

write_zeros - Insert 'NumZeros' nulls.

uint64_t tell() const

tell - Return the current offset with the file.

raw_ostream & write(unsigned char C)

A raw_ostream that writes to an SmallVector or SmallString.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

void validate(const Triple &TT, const FeatureBitset &FeatureBits)

bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)

@ fixup_riscv_pcrel_lo12_i

@ fixup_riscv_pcrel_lo12_s

@ fixup_riscv_nds_branch_10

@ fixup_riscv_qc_e_call_plt

@ fixup_riscv_qc_e_branch

initializer< Ty > init(const Ty &Val)

bool isRelocation(MCFixupKind FixupKind)

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

constexpr bool isUIntN(unsigned N, uint64_t x)

Checks if an unsigned integer fits into the given (dynamic) bit width.

uint16_t MCFixupKind

Extensible enumeration to represent the type of a fixup.

FunctionAddr VTableAddr Count

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

@ Success

The lock was released successfully.

@ FirstLiteralRelocationKind

@ FK_Data_8

A eight-byte fixup.

@ FK_Data_1

A one-byte fixup.

@ FK_Data_4

A four-byte fixup.

@ FK_Data_leb128

A leb128 fixup.

@ FK_Data_2

A two-byte fixup.

FunctionAddr VTableAddr uintptr_t uintptr_t Data

MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

Definition RISCVAsmBackend.cpp:958

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)

Utility function to encode a SLEB128 value to an output stream.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

Target independent information on a fixup kind.