LLVM: lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h Source File (original) (raw)
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13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
25
26namespace llvm {
27
28
29
31enum {
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250 return Desc.getNumOperands() - 5;
251
252 return Desc.getNumOperands() - 4;
253}
254
256 [[maybe_unused]] const uint64_t TSFlags = Desc.TSFlags;
258 return Desc.getNumOperands() - 3;
259}
260
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264
266
272 return Desc.getNumOperands() - Offset;
273}
274
277
278
279 return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
280}
281
290
293 return Desc.getNumOperands() - 1;
294}
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301 return -1;
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312}
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319 return -1;
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326}
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333 return Desc.getNumDefs() < Desc.getNumOperands() &&
335}
336
337
338enum {
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360};
361}
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464};
465}
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467
476
477
488
490 switch (RndMode) {
491 default:
494 return "rne";
496 return "rtz";
498 return "rdn";
500 return "rup";
502 return "rmm";
504 return "dyn";
505 }
506}
507
518
520 switch (Mode) {
521 default:
522 return false;
529 return true;
530 }
531}
532}
533
542
544 switch (RndMode) {
545 default:
546 llvm_unreachable("Unknown vector fixed-point rounding mode");
548 return "rnu";
550 return "rne";
552 return "rdn";
554 return "rod";
555 }
556}
557
566
568 switch (Mode) {
569 default:
570 return false;
575 return true;
576 }
577}
578}
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624 if (IsRV32Only && ActiveFeatures[RISCV::Feature64Bit])
625 return false;
626
628 return true;
630 }
631};
632
633#define GET_SysRegEncodings_DECL
634#define GET_SysRegsList_DECL
635#include "RISCVGenSearchableTables.inc"
636}
637
643
644#define GET_RISCVOpcodesList_DECL
645#include "RISCVGenSearchableTables.inc"
646}
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649
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675}
676
677namespace RISCVFeatures {
678
679
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681void validate(const Triple &TT, const FeatureBitset &FeatureBits);
682
684parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
685
686}
687
692
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712 assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
713 switch (EndReg.id()) {
714 case RISCV::X1:
716 case RISCV::X8:
718 case RISCV::X9:
720 case RISCV::X18:
722 case RISCV::X19:
724 case RISCV::X20:
726 case RISCV::X21:
728 case RISCV::X22:
730 case RISCV::X23:
732 case RISCV::X24:
734 case RISCV::X25:
736 case RISCV::X27:
738 default:
740 }
741}
742
744 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
745 "Unexpected number of registers");
746 if (NumRegs == 13)
748
750}
751
752inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
754 "Invalid Rlist");
756
758 ++NumRegs;
759
760 unsigned RegSize = IsRV64 ? 8 : 4;
762}
763
765}
766
767namespace RISCVVInversePseudosTable {
774
775#define GET_RISCVVInversePseudosTable_DECL
776#include "RISCVGenSearchableTables.inc"
777}
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853#define GET_RISCVVSSEGTable_DECL
854#define GET_RISCVVLSEGTable_DECL
855#define GET_RISCVVLXSEGTable_DECL
856#define GET_RISCVVSXSEGTable_DECL
857#define GET_RISCVVLETable_DECL
858#define GET_RISCVVSETable_DECL
859#define GET_RISCVVLXTable_DECL
860#define GET_RISCVVSXTable_DECL
861#define GET_RISCVNDSVLNTable_DECL
862#include "RISCVGenSearchableTables.inc"
863}
864
865}
866
867#endif
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
Wrapper class representing physical registers. Should be passed by value.
constexpr unsigned id() const
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI
Definition RISCVBaseInfo.h:650
@ ABI_ILP32D
Definition RISCVBaseInfo.h:653
@ ABI_LP64F
Definition RISCVBaseInfo.h:656
@ ABI_ILP32F
Definition RISCVBaseInfo.h:652
@ ABI_ILP32
Definition RISCVBaseInfo.h:651
@ ABI_Unknown
Definition RISCVBaseInfo.h:659
@ ABI_ILP32E
Definition RISCVBaseInfo.h:654
@ ABI_LP64E
Definition RISCVBaseInfo.h:658
@ ABI_LP64
Definition RISCVBaseInfo.h:655
@ ABI_LP64D
Definition RISCVBaseInfo.h:657
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
Definition RISCVBaseInfo.h:580
ExceptionFlag
Definition RISCVBaseInfo.h:581
@ NX
Definition RISCVBaseInfo.h:582
@ ALL
Definition RISCVBaseInfo.h:587
@ UF
Definition RISCVBaseInfo.h:583
@ OF
Definition RISCVBaseInfo.h:584
@ DZ
Definition RISCVBaseInfo.h:585
@ NV
Definition RISCVBaseInfo.h:586
Definition RISCVBaseInfo.h:478
static bool isValidRoundingMode(unsigned Mode)
Definition RISCVBaseInfo.h:519
static RoundingMode stringToRoundingMode(StringRef Str)
Definition RISCVBaseInfo.h:508
RoundingMode
Definition RISCVBaseInfo.h:479
@ RUP
Definition RISCVBaseInfo.h:483
@ DYN
Definition RISCVBaseInfo.h:485
@ RTZ
Definition RISCVBaseInfo.h:481
@ RDN
Definition RISCVBaseInfo.h:482
@ RMM
Definition RISCVBaseInfo.h:484
@ Invalid
Definition RISCVBaseInfo.h:486
@ RNE
Definition RISCVBaseInfo.h:480
static StringRef roundingModeToString(RoundingMode RndMode)
Definition RISCVBaseInfo.h:489
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
Definition RISCVBaseInfo.h:468
FenceField
Definition RISCVBaseInfo.h:469
@ W
Definition RISCVBaseInfo.h:473
@ R
Definition RISCVBaseInfo.h:472
@ O
Definition RISCVBaseInfo.h:471
@ I
Definition RISCVBaseInfo.h:470
Definition RISCVBaseInfo.h:30
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:291
static unsigned getTMOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:246
static bool usesMaskPolicy(uint64_t TSFlags)
Definition RISCVBaseInfo.h:193
static bool hasRoundModeOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:198
@ InstFormatCS
Definition RISCVBaseInfo.h:45
@ VLMulMask
Definition RISCVBaseInfo.h:72
@ TargetOverlapConstraintTypeMask
Definition RISCVBaseInfo.h:127
@ IsTiedPseudoShift
Definition RISCVBaseInfo.h:76
@ VMConstraint
Definition RISCVBaseInfo.h:68
@ TargetOverlapConstraintTypeShift
Definition RISCVBaseInfo.h:126
@ HasSEWOpShift
Definition RISCVBaseInfo.h:81
@ HasTKOpMask
Definition RISCVBaseInfo.h:160
@ InstFormatCB
Definition RISCVBaseInfo.h:47
@ HasTWidenOpShift
Definition RISCVBaseInfo.h:153
@ DestEEWMask
Definition RISCVBaseInfo.h:141
@ InstFormatCLB
Definition RISCVBaseInfo.h:50
@ UsesMaskPolicyMask
Definition RISCVBaseInfo.h:105
@ InstFormatS
Definition RISCVBaseInfo.h:36
@ UsesVXRMMask
Definition RISCVBaseInfo.h:118
@ InstFormatJ
Definition RISCVBaseInfo.h:39
@ InstFormatCU
Definition RISCVBaseInfo.h:49
@ HasVecPolicyOpShift
Definition RISCVBaseInfo.h:92
@ IsRVVWideningReductionShift
Definition RISCVBaseInfo.h:97
@ InstFormatShift
Definition RISCVBaseInfo.h:63
@ VS1Constraint
Definition RISCVBaseInfo.h:67
@ InstFormatI
Definition RISCVBaseInfo.h:35
@ InstFormatCL
Definition RISCVBaseInfo.h:44
@ ConstraintShift
Definition RISCVBaseInfo.h:65
@ IsSignExtendingOpWMask
Definition RISCVBaseInfo.h:112
@ AltFmtTypeMask
Definition RISCVBaseInfo.h:150
@ InstFormatPseudo
Definition RISCVBaseInfo.h:32
@ InstFormatR4
Definition RISCVBaseInfo.h:34
@ HasVLOpShift
Definition RISCVBaseInfo.h:87
@ DestEEWShift
Definition RISCVBaseInfo.h:140
@ VLMulShift
Definition RISCVBaseInfo.h:71
@ HasVLOpMask
Definition RISCVBaseInfo.h:88
@ IsRVVWideningReductionMask
Definition RISCVBaseInfo.h:98
@ ElementsDependOnMaskShift
Definition RISCVBaseInfo.h:132
@ HasTMOpMask
Definition RISCVBaseInfo.h:157
@ HasSEWOpMask
Definition RISCVBaseInfo.h:82
@ HasTKOpShift
Definition RISCVBaseInfo.h:159
@ InstFormatCSB
Definition RISCVBaseInfo.h:52
@ InstFormatCJ
Definition RISCVBaseInfo.h:48
@ ReadsPastVLMask
Definition RISCVBaseInfo.h:144
@ InstFormatQC_EJ
Definition RISCVBaseInfo.h:57
@ HasRoundModeOpShift
Definition RISCVBaseInfo.h:114
@ ConstraintMask
Definition RISCVBaseInfo.h:69
@ InstFormatCLH
Definition RISCVBaseInfo.h:51
@ InstFormatNDS_BRANCH_10
Definition RISCVBaseInfo.h:59
@ InstFormatU
Definition RISCVBaseInfo.h:38
@ InstFormatCIW
Definition RISCVBaseInfo.h:43
@ UsesVXRMShift
Definition RISCVBaseInfo.h:117
@ ElementsDependOnVLShift
Definition RISCVBaseInfo.h:129
@ ReadsPastVLShift
Definition RISCVBaseInfo.h:143
@ InstFormatB
Definition RISCVBaseInfo.h:37
@ HasTWidenOpMask
Definition RISCVBaseInfo.h:154
@ HasTMOpShift
Definition RISCVBaseInfo.h:156
@ InstFormatCA
Definition RISCVBaseInfo.h:46
@ HasVecPolicyOpMask
Definition RISCVBaseInfo.h:93
@ HasRoundModeOpMask
Definition RISCVBaseInfo.h:115
@ InstFormatOther
Definition RISCVBaseInfo.h:60
@ InstFormatCR
Definition RISCVBaseInfo.h:40
@ InstFormatQC_ES
Definition RISCVBaseInfo.h:58
@ IsTiedPseudoMask
Definition RISCVBaseInfo.h:77
@ InstFormatQC_EB
Definition RISCVBaseInfo.h:56
@ ElementsDependOnMaskMask
Definition RISCVBaseInfo.h:133
@ InstFormatCSS
Definition RISCVBaseInfo.h:42
@ VS2Constraint
Definition RISCVBaseInfo.h:66
@ InstFormatQC_EAI
Definition RISCVBaseInfo.h:54
@ UsesMaskPolicyShift
Definition RISCVBaseInfo.h:104
@ ElementsDependOnVLMask
Definition RISCVBaseInfo.h:130
@ IsSignExtendingOpWShift
Definition RISCVBaseInfo.h:111
@ InstFormatR
Definition RISCVBaseInfo.h:33
@ InstFormatMask
Definition RISCVBaseInfo.h:62
@ InstFormatCSH
Definition RISCVBaseInfo.h:53
@ InstFormatCI
Definition RISCVBaseInfo.h:41
@ InstFormatQC_EI
Definition RISCVBaseInfo.h:55
@ AltFmtTypeShift
Definition RISCVBaseInfo.h:149
static bool readsPastVL(uint64_t TSFlags)
Definition RISCVBaseInfo.h:224
static bool hasTWidenOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:229
@ MO_None
Definition RISCVBaseInfo.h:339
@ MO_PCREL_HI
Definition RISCVBaseInfo.h:344
@ MO_PCREL_LO
Definition RISCVBaseInfo.h:343
@ MO_TLSDESC_CALL
Definition RISCVBaseInfo.h:354
@ MO_TPREL_HI
Definition RISCVBaseInfo.h:347
@ MO_CALL
Definition RISCVBaseInfo.h:340
@ MO_TLSDESC_ADD_LO
Definition RISCVBaseInfo.h:353
@ MO_DIRECT_FLAG_MASK
Definition RISCVBaseInfo.h:359
@ MO_TLS_GOT_HI
Definition RISCVBaseInfo.h:349
@ MO_GOT_HI
Definition RISCVBaseInfo.h:345
@ MO_TLSDESC_LOAD_LO
Definition RISCVBaseInfo.h:352
@ MO_TPREL_LO
Definition RISCVBaseInfo.h:346
@ MO_HI
Definition RISCVBaseInfo.h:342
@ MO_TLS_GD_HI
Definition RISCVBaseInfo.h:350
@ MO_LO
Definition RISCVBaseInfo.h:341
@ MO_TLSDESC_HI
Definition RISCVBaseInfo.h:351
@ MO_TPREL_ADD
Definition RISCVBaseInfo.h:348
static bool isTiedPseudo(uint64_t TSFlags)
Definition RISCVBaseInfo.h:173
static RISCVVType::VLMUL getLMul(uint64_t TSFlags)
Definition RISCVBaseInfo.h:169
static unsigned getTKOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:255
static unsigned getVLOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:261
static AltFmtType getAltFmtType(uint64_t TSFlags)
Definition RISCVBaseInfo.h:203
static unsigned getFormat(uint64_t TSFlags)
Definition RISCVBaseInfo.h:165
static bool hasTKOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:235
static bool hasVLOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:181
static MCRegister getTailExpandUseRegNo(const FeatureBitset &FeatureBits)
Definition RISCVBaseInfo.h:276
static bool elementsDependOnMask(uint64_t TSFlags)
Definition RISCVBaseInfo.h:218
static int getFRMOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:298
static bool hasTMOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:233
static int getVXRMOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:316
static unsigned getTNOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:237
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:185
static bool usesVXRM(uint64_t TSFlags)
Definition RISCVBaseInfo.h:208
AltFmtType
Definition RISCVBaseInfo.h:202
@ DontCare
Definition RISCVBaseInfo.h:202
@ AltFmt
Definition RISCVBaseInfo.h:202
@ NotAltFmt
Definition RISCVBaseInfo.h:202
static bool isRVVWideningReduction(uint64_t TSFlags)
Definition RISCVBaseInfo.h:189
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:282
static bool elementsDependOnVL(uint64_t TSFlags)
Definition RISCVBaseInfo.h:212
static bool hasSEWOp(uint64_t TSFlags)
Definition RISCVBaseInfo.h:177
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
Definition RISCVBaseInfo.h:332
Definition RISCVBaseInfo.h:595
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
Definition RISCVBaseInfo.h:363
OperandType
Definition RISCVBaseInfo.h:364
@ OPERAND_UIMMLOG2XLEN_NONZERO
Definition RISCVBaseInfo.h:397
@ OPERAND_RVKRNUM
Definition RISCVBaseInfo.h:422
@ OPERAND_SIMM16_NONZERO
Definition RISCVBaseInfo.h:416
@ OPERAND_SEW_MASK
Definition RISCVBaseInfo.h:443
@ OPERAND_SIMM5_PLUS1
Definition RISCVBaseInfo.h:406
@ OPERAND_UIMM20_LUI
Definition RISCVBaseInfo.h:452
@ OPERAND_SIMM12_LSB00000
Definition RISCVBaseInfo.h:414
@ OPERAND_UIMM3
Definition RISCVBaseInfo.h:369
@ OPERAND_VTYPEI11
Definition RISCVBaseInfo.h:421
@ OPERAND_UIMM8_LSB000
Definition RISCVBaseInfo.h:385
@ OPERAND_UIMM1
Definition RISCVBaseInfo.h:366
@ OPERAND_UIMM20_AUIPC
Definition RISCVBaseInfo.h:453
@ OPERAND_FRMARG
Definition RISCVBaseInfo.h:431
@ OPERAND_UIMM4
Definition RISCVBaseInfo.h:370
@ OPERAND_UIMM5_LSB0
Definition RISCVBaseInfo.h:376
@ OPERAND_SIMM5
Definition RISCVBaseInfo.h:404
@ OPERAND_SIMM11
Definition RISCVBaseInfo.h:413
@ OPERAND_SIMM10_UNSIGNED
Definition RISCVBaseInfo.h:412
@ OPERAND_VEC_POLICY
Definition RISCVBaseInfo.h:439
@ OPERAND_STACKADJ
Definition RISCVBaseInfo.h:428
@ OPERAND_UIMM32
Definition RISCVBaseInfo.h:398
@ OPERAND_UIMM8
Definition RISCVBaseInfo.h:384
@ OPERAND_SIMM26
Definition RISCVBaseInfo.h:418
@ OPERAND_IMM5_ZIBI
Definition RISCVBaseInfo.h:403
@ OPERAND_FIRST_RISCV_IMM
Definition RISCVBaseInfo.h:365
@ OPERAND_RLIST
Definition RISCVBaseInfo.h:426
@ OPERAND_UIMM6
Definition RISCVBaseInfo.h:378
@ OPERAND_UIMM48
Definition RISCVBaseInfo.h:399
@ OPERAND_CLUI_IMM
Definition RISCVBaseInfo.h:419
@ OPERAND_UIMM5_NONZERO
Definition RISCVBaseInfo.h:372
@ OPERAND_UIMM16_NONZERO
Definition RISCVBaseInfo.h:395
@ OPERAND_RLIST_S0
Definition RISCVBaseInfo.h:427
@ OPERAND_LAST_RISCV_IMM
Definition RISCVBaseInfo.h:450
@ OPERAND_SIMM6_NONZERO
Definition RISCVBaseInfo.h:408
@ OPERAND_SIMM20_LI
Definition RISCVBaseInfo.h:417
@ OPERAND_XSFMM_TWIDEN
Definition RISCVBaseInfo.h:449
@ OPERAND_UIMM14_LSB00
Definition RISCVBaseInfo.h:393
@ OPERAND_UIMM2_LSB0
Definition RISCVBaseInfo.h:368
@ OPERAND_COND_CODE
Definition RISCVBaseInfo.h:435
@ OPERAND_UIMM11
Definition RISCVBaseInfo.h:391
@ OPERAND_UIMMLOG2XLEN
Definition RISCVBaseInfo.h:396
@ OPERAND_UIMM7_LSB000
Definition RISCVBaseInfo.h:382
@ OPERAND_XSFMM_VTYPE
Definition RISCVBaseInfo.h:447
@ OPERAND_VEC_RM
Definition RISCVBaseInfo.h:445
@ OPERAND_UIMM7_LSB00
Definition RISCVBaseInfo.h:381
@ OPERAND_UIMM5_SLIST
Definition RISCVBaseInfo.h:377
@ OPERAND_UIMM9_LSB000
Definition RISCVBaseInfo.h:387
@ OPERAND_UIMM8_GE32
Definition RISCVBaseInfo.h:386
@ OPERAND_SIMM6
Definition RISCVBaseInfo.h:407
@ OPERAND_UIMM10
Definition RISCVBaseInfo.h:389
@ OPERAND_RTZARG
Definition RISCVBaseInfo.h:433
@ OPERAND_SIMM8_UNSIGNED
Definition RISCVBaseInfo.h:409
@ OPERAND_UIMM10_LSB00_NONZERO
Definition RISCVBaseInfo.h:390
@ OPERAND_UIMM64
Definition RISCVBaseInfo.h:400
@ OPERAND_FOUR
Definition RISCVBaseInfo.h:402
@ OPERAND_THREE
Definition RISCVBaseInfo.h:401
@ OPERAND_RVKRNUM_1_10
Definition RISCVBaseInfo.h:424
@ OPERAND_UIMM12
Definition RISCVBaseInfo.h:392
@ OPERAND_SEW
Definition RISCVBaseInfo.h:441
@ OPERAND_SIMM5_NONZERO
Definition RISCVBaseInfo.h:405
@ OPERAND_SIMM16
Definition RISCVBaseInfo.h:415
@ OPERAND_UIMM16
Definition RISCVBaseInfo.h:394
@ OPERAND_AVL
Definition RISCVBaseInfo.h:463
@ OPERAND_RVKRNUM_0_7
Definition RISCVBaseInfo.h:423
@ OPERAND_UIMM9
Definition RISCVBaseInfo.h:388
@ OPERAND_SIMM10_LSB0000_NONZERO
Definition RISCVBaseInfo.h:411
@ OPERAND_UIMM8_LSB00
Definition RISCVBaseInfo.h:383
@ OPERAND_UIMM5_PLUS1
Definition RISCVBaseInfo.h:374
@ OPERAND_UIMM5_GT3
Definition RISCVBaseInfo.h:373
@ OPERAND_SIMM12_LO
Definition RISCVBaseInfo.h:456
@ OPERAND_VTYPEI10
Definition RISCVBaseInfo.h:420
@ OPERAND_RVKRNUM_2_14
Definition RISCVBaseInfo.h:425
@ OPERAND_UIMM6_LSB0
Definition RISCVBaseInfo.h:379
@ OPERAND_UIMM5
Definition RISCVBaseInfo.h:371
@ OPERAND_BARE_SIMM32
Definition RISCVBaseInfo.h:458
@ OPERAND_ATOMIC_ORDERING
Definition RISCVBaseInfo.h:437
@ OPERAND_UIMM5_GE6_PLUS1
Definition RISCVBaseInfo.h:375
@ OPERAND_SIMM10
Definition RISCVBaseInfo.h:410
@ OPERAND_UIMM7
Definition RISCVBaseInfo.h:380
@ OPERAND_UIMM2
Definition RISCVBaseInfo.h:367
Definition RISCVBaseInfo.h:688
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
Definition RISCVBaseInfo.h:534
static bool isValidRoundingMode(unsigned Mode)
Definition RISCVBaseInfo.h:567
RoundingMode
Definition RISCVBaseInfo.h:535
@ ROD
Definition RISCVBaseInfo.h:539
@ Invalid
Definition RISCVBaseInfo.h:540
@ RNE
Definition RISCVBaseInfo.h:537
@ RNU
Definition RISCVBaseInfo.h:536
@ RDN
Definition RISCVBaseInfo.h:538
static RoundingMode stringToRoundingMode(StringRef Str)
Definition RISCVBaseInfo.h:558
static StringRef roundingModeToString(RoundingMode RndMode)
Definition RISCVBaseInfo.h:543
Definition RISCVBaseInfo.h:693
unsigned encodeRegList(MCRegister EndReg, bool IsRVE=false)
Definition RISCVBaseInfo.h:711
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64)
Definition RISCVBaseInfo.h:752
RLISTENCODE
Definition RISCVBaseInfo.h:694
@ RA_S0_S5
Definition RISCVBaseInfo.h:701
@ RA_S0_S1
Definition RISCVBaseInfo.h:697
@ RA_S0_S8
Definition RISCVBaseInfo.h:704
@ RA_S0_S2
Definition RISCVBaseInfo.h:698
@ RA_S0_S9
Definition RISCVBaseInfo.h:705
@ RA_S0_S6
Definition RISCVBaseInfo.h:702
@ RA_S0_S11
Definition RISCVBaseInfo.h:707
@ RA_S0_S7
Definition RISCVBaseInfo.h:703
@ INVALID_RLIST
Definition RISCVBaseInfo.h:708
@ RA_S0
Definition RISCVBaseInfo.h:696
@ RA_S0_S3
Definition RISCVBaseInfo.h:699
@ RA_S0_S4
Definition RISCVBaseInfo.h:700
@ RA
Definition RISCVBaseInfo.h:695
void printRegList(unsigned RlistEncode, raw_ostream &OS)
static unsigned encodeRegListNumRegs(unsigned NumRegs)
Definition RISCVBaseInfo.h:743
This is an optimization pass for GlobalISel generic memory operations.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition RISCVBaseInfo.h:639
char Name[10]
Definition RISCVBaseInfo.h:640
uint8_t Value
Definition RISCVBaseInfo.h:641
Definition RISCVBaseInfo.h:605
const char Name[32]
Definition RISCVBaseInfo.h:606
FeatureBitset FeaturesRequired
Definition RISCVBaseInfo.h:617
bool IsDeprecatedName
Definition RISCVBaseInfo.h:620
unsigned Encoding
Definition RISCVBaseInfo.h:607
bool IsAltName
Definition RISCVBaseInfo.h:619
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const
Definition RISCVBaseInfo.h:622
bool IsRV32Only
Definition RISCVBaseInfo.h:618
Definition RISCVBaseInfo.h:768
uint16_t BaseInstr
Definition RISCVBaseInfo.h:770
uint8_t SEW
Definition RISCVBaseInfo.h:772
uint16_t Pseudo
Definition RISCVBaseInfo.h:769
uint8_t VLMul
Definition RISCVBaseInfo.h:771
Definition RISCVBaseInfo.h:845
uint16_t Masked
Definition RISCVBaseInfo.h:846
uint16_t Unsigned
Definition RISCVBaseInfo.h:847
uint16_t Log2SEW
Definition RISCVBaseInfo.h:848
uint16_t LMUL
Definition RISCVBaseInfo.h:849
uint16_t Pseudo
Definition RISCVBaseInfo.h:850
Definition RISCVBaseInfo.h:819
uint16_t Masked
Definition RISCVBaseInfo.h:820
uint16_t LMUL
Definition RISCVBaseInfo.h:824
uint16_t FF
Definition RISCVBaseInfo.h:822
uint16_t Strided
Definition RISCVBaseInfo.h:821
uint16_t Pseudo
Definition RISCVBaseInfo.h:825
uint16_t Log2SEW
Definition RISCVBaseInfo.h:823
Definition RISCVBaseInfo.h:780
uint16_t Log2SEW
Definition RISCVBaseInfo.h:785
uint16_t NF
Definition RISCVBaseInfo.h:781
uint16_t FF
Definition RISCVBaseInfo.h:784
uint16_t LMUL
Definition RISCVBaseInfo.h:786
uint16_t Strided
Definition RISCVBaseInfo.h:783
uint16_t Masked
Definition RISCVBaseInfo.h:782
uint16_t Pseudo
Definition RISCVBaseInfo.h:787
Definition RISCVBaseInfo.h:790
uint16_t LMUL
Definition RISCVBaseInfo.h:795
uint16_t IndexLMUL
Definition RISCVBaseInfo.h:796
uint16_t Ordered
Definition RISCVBaseInfo.h:793
uint16_t NF
Definition RISCVBaseInfo.h:791
uint16_t Masked
Definition RISCVBaseInfo.h:792
uint16_t Log2SEW
Definition RISCVBaseInfo.h:794
uint16_t Pseudo
Definition RISCVBaseInfo.h:797
Definition RISCVBaseInfo.h:836
uint16_t Log2SEW
Definition RISCVBaseInfo.h:839
uint16_t IndexLMUL
Definition RISCVBaseInfo.h:841
uint16_t LMUL
Definition RISCVBaseInfo.h:840
uint16_t Masked
Definition RISCVBaseInfo.h:837
uint16_t Pseudo
Definition RISCVBaseInfo.h:842
uint16_t Ordered
Definition RISCVBaseInfo.h:838
Definition RISCVBaseInfo.h:828
uint16_t LMUL
Definition RISCVBaseInfo.h:832
uint16_t Pseudo
Definition RISCVBaseInfo.h:833
uint16_t Log2SEW
Definition RISCVBaseInfo.h:831
uint16_t Masked
Definition RISCVBaseInfo.h:829
uint16_t Strided
Definition RISCVBaseInfo.h:830
Definition RISCVBaseInfo.h:800
uint16_t Log2SEW
Definition RISCVBaseInfo.h:804
uint16_t Pseudo
Definition RISCVBaseInfo.h:806
uint16_t LMUL
Definition RISCVBaseInfo.h:805
uint16_t Strided
Definition RISCVBaseInfo.h:803
uint16_t NF
Definition RISCVBaseInfo.h:801
uint16_t Masked
Definition RISCVBaseInfo.h:802
Definition RISCVBaseInfo.h:809
uint16_t NF
Definition RISCVBaseInfo.h:810
uint16_t Pseudo
Definition RISCVBaseInfo.h:816
uint16_t LMUL
Definition RISCVBaseInfo.h:814
uint16_t Ordered
Definition RISCVBaseInfo.h:812
uint16_t IndexLMUL
Definition RISCVBaseInfo.h:815
uint16_t Masked
Definition RISCVBaseInfo.h:811
uint16_t Log2SEW
Definition RISCVBaseInfo.h:813