RISCVCustomBehaviour.cpp Source File (original) (raw)

23#define DEBUG_TYPE "llvm-mca-riscv-custombehaviour"

34#define GET_RISCVBaseVXMemOpTable_IMPL

35#include "RISCVGenSearchableTables.inc"

36}

38namespace llvm {

39namespace mca {

46 .Cases({"M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"}, true)

48}

54 "Cannot get LMUL because invalid Data value");

57 .Case("M1", 0b000)

58 .Case("M2", 0b001)

59 .Case("M4", 0b010)

60 .Case("M8", 0b011)

61 .Case("MF2", 0b111)

62 .Case("MF4", 0b110)

63 .Case("MF8", 0b101);

64}

71 .Cases({"E8", "E16", "E32", "E64"}, true)

73}

81 .Case("E8", 8)

82 .Case("E16", 16)

83 .Case("E32", 32)

84 .Case("E64", 64);

85}

99 LDBG() << "RVCB: Bad data for instrument kind " << Desc << ": " << Data

100 << '\n';

101 return nullptr;

102 }

103 return std::make_unique(Data);

104 }

105

108 LDBG() << "RVCB: Bad data for instrument kind " << Desc << ": " << Data

109 << '\n';

110 return nullptr;

111 }

112 return std::make_unique(Data);

113 }

114

115 LDBG() << "RVCB: Creating default instrument for Desc: " << Desc << '\n';

117}

118

121 if (Inst.getOpcode() == RISCV::VSETVLI ||

122 Inst.getOpcode() == RISCV::VSETIVLI) {

123 LDBG() << "RVCB: Found VSETVLI and creating instrument for it: " << Inst

124 << "\n";

127

129 switch (VLMUL) {

131 LMUL = "M1";

132 break;

134 LMUL = "M2";

135 break;

137 LMUL = "M4";

138 break;

140 LMUL = "M8";

141 break;

143 LMUL = "MF2";

144 break;

146 LMUL = "MF4";

147 break;

149 LMUL = "MF8";

150 break;

152 llvm_unreachable("Cannot create instrument for LMUL_RESERVED");

153 }

157

160 switch (SEW) {

161 case 8:

162 SEWStr = "E8";

163 break;

164 case 16:

165 SEWStr = "E16";

166 break;

167 case 32:

168 SEWStr = "E32";

169 break;

170 case 64:

171 SEWStr = "E64";

172 break;

173 default:

175 }

178

179 return Instruments;

180 }

182}

183

184static std::pair<uint8_t, uint8_t>

187 switch (Opcode) {

188 case RISCV::VLM_V:

189 case RISCV::VSM_V:

190 case RISCV::VLE8_V:

191 case RISCV::VSE8_V:

192 case RISCV::VLSE8_V:

193 case RISCV::VSSE8_V:

194 EEW = 8;

195 break;

196 case RISCV::VLE16_V:

197 case RISCV::VSE16_V:

198 case RISCV::VLSE16_V:

199 case RISCV::VSSE16_V:

200 EEW = 16;

201 break;

202 case RISCV::VLE32_V:

203 case RISCV::VSE32_V:

204 case RISCV::VLSE32_V:

205 case RISCV::VSSE32_V:

206 EEW = 32;

207 break;

208 case RISCV::VLE64_V:

209 case RISCV::VSE64_V:

210 case RISCV::VLSE64_V:

211 case RISCV::VSSE64_V:

212 EEW = 64;

213 break;

214 default:

216 }

217

218 auto EMUL =

220 if (!EEW)

222 return std::make_pair(EEW, *EMUL);

223}

224

226 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V ||

227 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V ||

228 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V ||

229 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V ||

230 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V ||

231 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V ||

232 Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V ||

233 Opcode == RISCV::VLSE32_V || Opcode == RISCV::VSSE32_V ||

234 Opcode == RISCV::VLSE64_V || Opcode == RISCV::VSSE64_V;

235}

236

240 unsigned short Opcode = MCI.getOpcode();

241 unsigned SchedClassID = MCII.get(Opcode).getSchedClass();

242

243

246 for (auto &I : IVec) {

251 }

252

253

254

255 if (!LI) {

256 LDBG() << "RVCB: Did not use instrumentation to override Opcode.\n";

257 return SchedClassID;

258 }

260

261

262

263

265

266 std::optional VPOpcode;

267 if (const auto *VXMO = RISCV::getVXMemOpInfo(Opcode)) {

268

269

270 unsigned IndexEMUL = ((1 << VXMO->Log2IdxEEW) * LMUL) / SEW;

271

272 if (!VXMO->NF) {

273

274 if (VXMO->IsStore) {

275 if (const auto *VXP = RISCV::getVSXPseudo(

276 0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,

277 IndexEMUL))

278 VPOpcode = VXP->Pseudo;

279 } else {

280 if (const auto *VXP = RISCV::getVLXPseudo(

281 0, VXMO->IsOrdered, VXMO->Log2IdxEEW, LMUL,

282 IndexEMUL))

283 VPOpcode = VXP->Pseudo;

284 }

285 } else {

286

287 if (VXMO->IsStore) {

288 if (const auto *VXP =

289 RISCV::getVSXSEGPseudo(VXMO->NF, 0, VXMO->IsOrdered,

290 VXMO->Log2IdxEEW, LMUL, IndexEMUL))

291 VPOpcode = VXP->Pseudo;

292 } else {

293 if (const auto *VXP =

294 RISCV::getVLXSEGPseudo(VXMO->NF, 0, VXMO->IsOrdered,

295 VXMO->Log2IdxEEW, LMUL, IndexEMUL))

296 VPOpcode = VXP->Pseudo;

297 }

298 }

301 auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW);

302 if (const auto *RVV =

303 RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW))

304 VPOpcode = RVV->Pseudo;

305 } else {

306

307 const auto *RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);

308

309 if ( RVV )

310 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);

311

313 VPOpcode = RVV->Pseudo;

314 }

315

316

317 if (!VPOpcode) {

318 LDBG() << "RVCB: Could not find PseudoInstruction for Opcode "

319 << MCII.getName(Opcode)

320 << ", LMUL=" << (LI ? LI->getData() : "Unspecified")

321 << ", SEW=" << (SI ? SI->getData() : "Unspecified")

322 << ". Ignoring instrumentation and using original SchedClassID="

323 << SchedClassID << '\n';

324 return SchedClassID;

325 }

326

327

328 LDBG() << "RVCB: Found Pseudo Instruction for Opcode " << MCII.getName(Opcode)

329 << ", LMUL=" << LI->getData()

330 << ", SEW=" << (SI ? SI->getData() : "Unspecified")

331 << ". Overriding original SchedClassID=" << SchedClassID << " with "

332 << MCII.getName(*VPOpcode) << '\n';

333 return MCII.get(*VPOpcode).getSchedClass();

334}

335

336}

337}

338

339using namespace llvm;

340using namespace mca;

341

347

348

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define LLVM_EXTERNAL_VISIBILITY

#define LDBG(...)

LDBG() is a macro that can be used as a raw_ostream for debugging.

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMCA()

Extern function to initialize the targets for the RISC-V backend.

Definition RISCVCustomBehaviour.cpp:350

static InstrumentManager * createRISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)

Definition RISCVCustomBehaviour.cpp:343

This file defines the RISCVCustomBehaviour class which inherits from CustomBehaviour.

Instances of this class represent a single low-level machine instruction.

unsigned getOpcode() const

const MCOperand & getOperand(unsigned i) const

Interface to description of machine instruction set.

Generic base class for all target subtargets.

reference emplace_back(ArgTypes &&... Args)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

StringSwitch & Cases(std::initializer_list< StringLiteral > CaseStrings, T Value)

The instances of the Type class are immutable: once they are created, they are never changed.

This class allows targets to optionally customize the logic that resolves scheduling class IDs.

virtual UniqueInstrument createInstrument(StringRef Desc, StringRef Data)

Allocate an Instrument, and return a unique pointer to it.

virtual bool supportsInstrumentType(StringRef Type) const

StringRef getData() const

bool supportsInstrumentType(StringRef Type) const override

Definition RISCVCustomBehaviour.cpp:87

unsigned getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI, const SmallVector< Instrument * > &IVec) const override

Using the Instrument, returns a SchedClassID to use instead of the SchedClassID that belongs to the M...

Definition RISCVCustomBehaviour.cpp:237

UniqueInstrument createInstrument(StringRef Desc, StringRef Data) override

Create a Instrument for RISC-V target.

Definition RISCVCustomBehaviour.cpp:95

SmallVector< UniqueInstrument > createInstruments(const MCInst &Inst) override

Return a list of unique pointers to Instruments, where each Instrument is allocated by this function.

Definition RISCVCustomBehaviour.cpp:120

uint8_t getLMUL() const

Definition RISCVCustomBehaviour.cpp:50

static bool isDataValid(StringRef Data)

Definition RISCVCustomBehaviour.cpp:43

static const StringRef DESC_NAME

static bool isDataValid(StringRef Data)

Definition RISCVCustomBehaviour.cpp:68

static const StringRef DESC_NAME

uint8_t getSEW() const

Definition RISCVCustomBehaviour.cpp:75

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

LLVM_ABI std::optional< VLMUL > getSameRatioLMUL(unsigned Ratio, unsigned EEW)

LLVM_ABI unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul)

static unsigned getSEW(unsigned VType)

static VLMUL getVLMUL(unsigned VType)

std::unique_ptr< Instrument > UniqueInstrument

static bool opcodeHasEEWAndEMULInfo(unsigned short Opcode)

Definition RISCVCustomBehaviour.cpp:225

static std::pair< uint8_t, uint8_t > getEEWAndEMUL(unsigned Opcode, RISCVVType::VLMUL LMUL, uint8_t SEW)

Definition RISCVCustomBehaviour.cpp:185

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheRISCV32Target()

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

FunctionAddr VTableAddr uintptr_t uintptr_t Data

Target & getTheRISCV64Target()

@ Default

The result values are uniform if and only if all operands are uniform.

unsigned NF

Definition RISCVCustomBehaviour.cpp:30

unsigned Log2IdxEEW

Definition RISCVCustomBehaviour.cpp:27

unsigned IsOrdered

Definition RISCVCustomBehaviour.cpp:28

unsigned IsStore

Definition RISCVCustomBehaviour.cpp:29

unsigned BaseInstr

Definition RISCVCustomBehaviour.cpp:31

static void RegisterInstrumentManager(Target &T, Target::InstrumentManagerCtorTy Fn)

RegisterInstrumentManager - Register an InstrumentManager implementation for the given target.