RISCVMakeCompressible.cpp Source File (original) (raw)

75using namespace llvm;

77#define DEBUG_TYPE "riscv-make-compressible"

78#define RISCV_COMPRESS_INSTRS_NAME "RISC-V Make Compressible"

80namespace {

83 static char ID;

90};

91}

93char RISCVMakeCompressibleOpt::ID = 0;

94 INITIALIZE_PASS(RISCVMakeCompressibleOpt, "riscv-make-compressible",

98static unsigned log2LdstWidth(unsigned Opcode) {

99 switch (Opcode) {

100 default:

102 case RISCV::LBU:

103 case RISCV::SB:

104 return 0;

105 case RISCV::LH:

106 case RISCV::LH_INX:

107 case RISCV::LHU:

108 case RISCV::SH:

109 case RISCV::SH_INX:

110 return 1;

111 case RISCV::LW:

112 case RISCV::LW_INX:

113 case RISCV::SW:

114 case RISCV::SW_INX:

115 case RISCV::FLW:

116 case RISCV::FSW:

117 return 2;

118 case RISCV::LD:

119 case RISCV::LD_RV32:

120 case RISCV::SD:

121 case RISCV::SD_RV32:

122 case RISCV::FLD:

123 case RISCV::FSD:

124 return 3;

125 }

126}

127

128

130 switch (Opcode) {

131 default:

133 case RISCV::LBU:

134 case RISCV::SB:

136 case RISCV::LH:

137 case RISCV::LH_INX:

138 case RISCV::LHU:

139 case RISCV::SH:

140 case RISCV::SH_INX:

142 case RISCV::LW:

143 case RISCV::LW_INX:

144 case RISCV::SW:

145 case RISCV::SW_INX:

146 case RISCV::FLW:

147 case RISCV::FSW:

148 case RISCV::LD:

149 case RISCV::LD_RV32:

150 case RISCV::SD:

151 case RISCV::SD_RV32:

152 case RISCV::FLD:

153 case RISCV::FSD:

155 }

156}

157

158

159

161 return offsetMask(Opcode) << log2LdstWidth(Opcode);

162}

163

164

165

167

168 switch (log2LdstWidth(Opcode)) {

169 case 2:

171 case 3:

173 }

174 return false;

175}

176

177

178

179

184

185

187 return RISCV::GPRCRegClass.contains(Reg) ||

188 RISCV::GPRF16CRegClass.contains(Reg) ||

189 RISCV::GPRF32CRegClass.contains(Reg) ||

190 RISCV::FPR32CRegClass.contains(Reg) ||

191 RISCV::FPR64CRegClass.contains(Reg) ||

192 RISCV::GPRPairCRegClass.contains(Reg);

193}

194

195

198

199 switch (MI.getOpcode()) {

200 default:

201 return false;

202 case RISCV::LBU:

203 case RISCV::LH:

204 case RISCV::LH_INX:

205 case RISCV::LHU:

206 return STI.hasStdExtZcb();

207 case RISCV::LW:

208 case RISCV::LW_INX:

209 case RISCV::LD:

210 return STI.hasStdExtZca();

211 case RISCV::LD_RV32:

212 return STI.hasStdExtZclsd();

213 case RISCV::FLW:

215 case RISCV::FLD:

217 }

218}

219

220

223

224 switch (MI.getOpcode()) {

225 default:

226 return false;

227 case RISCV::SB:

228 case RISCV::SH:

229 case RISCV::SH_INX:

230 return STI.hasStdExtZcb();

231 case RISCV::SW:

232 case RISCV::SW_INX:

233 case RISCV::SD:

234 return STI.hasStdExtZca();

235 case RISCV::SD_RV32:

236 return STI.hasStdExtZclsd();

237 case RISCV::FSW:

239 case RISCV::FSD:

241 }

242}

243

244

245

246

247

248

249

250

251

252

253

254

255

257 const unsigned Opcode = MI.getOpcode();

258

261 if (!MOImm.isImm())

263

267

268

269

273 } else {

274 Register SrcDest = MI.getOperand(0).getReg();

277

278

279

280 if ((!BaseCompressed || NewBaseAdjust) && SrcDestCompressed)

282

283

284

285

286

287

289 if (!SrcDestCompressed && (BaseCompressed || SrcDest == Base) &&

290 !NewBaseAdjust)

291 return RegImmPair(SrcDest, NewBaseAdjust);

292 }

293 }

294 }

296}

297

298

299

300

301

302

303

309 MBB.getParent()->getSubtarget().getRegisterInfo();

310

312 E = MBB.instr_end();

313 I != E; ++I) {

315

316

317

319 if (CandidateRegImm.Reg == RegImm.Reg && CandidateRegImm.Imm == RegImm.Imm)

321

322

323

324

325

326

327 if (MI.modifiesRegister(RegImm.Reg, TRI))

328 break;

329 }

330

331

332

333

334

335

336 unsigned CopyCost = RISCV::GPRPairRegClass.contains(RegImm.Reg) ? 2 : 1;

337 assert((RegImm.Imm == 0 || CopyCost == 1) && "GPRPair should have zero imm");

338 if (MIs.size() <= CopyCost || (RegImm.Imm != 0 && MIs.size() <= 2))

340

341

342

344

345

346 if (RISCV::GPRRegClass.contains(RegImm.Reg))

347 RCToScavenge = &RISCV::GPRCRegClass;

348 else if (RISCV::GPRF16RegClass.contains(RegImm.Reg))

349 RCToScavenge = &RISCV::GPRF16CRegClass;

350 else if (RISCV::GPRF32RegClass.contains(RegImm.Reg))

351 RCToScavenge = &RISCV::GPRF32CRegClass;

352 else if (RISCV::FPR32RegClass.contains(RegImm.Reg))

353 RCToScavenge = &RISCV::FPR32CRegClass;

354 else if (RISCV::FPR64RegClass.contains(RegImm.Reg))

355 RCToScavenge = &RISCV::FPR64CRegClass;

356 else if (RISCV::GPRPairRegClass.contains(RegImm.Reg))

357 RCToScavenge = &RISCV::GPRPairCRegClass;

358 else

360

362 RS.enterBasicBlockEnd(MBB);

363 RS.backward(std::next(MIs.back()->getIterator()));

364 return RS.scavengeRegisterBackwards(*RCToScavenge, FirstMI.getIterator(),

365 false, 0,

366 false);

367}

368

369

372 unsigned Opcode = MI.getOpcode();

373

374

375

377 "Unsupported instruction for this optimization.");

378

379 int SkipN = 0;

380

381

382

383

385 SkipN = 1;

386

387

389 if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {

390

391

392

393

394

395 if (MO.isDef()) {

397 continue;

398 }

399

400 MO.setReg(NewReg);

401 }

402

403

406 MOImm.setImm(NewOffset);

407}

408

409bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {

410

412 return false;

413

414 const RISCVSubtarget &STI = Fn.getSubtarget();

416

417

418 if (!STI.hasStdExtZca())

419 return false;

420

421 for (MachineBasicBlock &MBB : Fn) {

423 for (MachineInstr &MI : MBB) {

424

425

428 continue;

429

430

431

432

433 SmallVector<MachineInstr *, 8> MIs;

435 if (!NewReg)

436 continue;

437

438

444 } else {

447 false);

448 }

449

450

451

452

453

454

455 for (MachineInstr *UpdateMI : MIs)

457 }

458 }

459 return true;

460}

461

462

464 return new RISCVMakeCompressibleOpt();

465}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

const HexagonInstrInfo * TII

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static bool isCompressibleLoad(const MachineInstr &MI)

Definition RISCVMakeCompressible.cpp:196

#define RISCV_COMPRESS_INSTRS_NAME

Definition RISCVMakeCompressible.cpp:78

static unsigned offsetMask(unsigned Opcode)

Definition RISCVMakeCompressible.cpp:129

static bool isCompressibleStore(const MachineInstr &MI)

Definition RISCVMakeCompressible.cpp:221

static uint8_t compressedLDSTOffsetMask(unsigned Opcode)

Definition RISCVMakeCompressible.cpp:160

static bool isCompressedReg(Register Reg)

Definition RISCVMakeCompressible.cpp:186

static Register analyzeCompressibleUses(MachineInstr &FirstMI, RegImmPair RegImm, SmallVectorImpl< MachineInstr * > &MIs)

Definition RISCVMakeCompressible.cpp:304

static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode)

Definition RISCVMakeCompressible.cpp:180

static void updateOperands(MachineInstr &MI, RegImmPair OldRegImm, Register NewReg)

Definition RISCVMakeCompressible.cpp:370

static bool compressibleSPOffset(int64_t Offset, unsigned Opcode)

Definition RISCVMakeCompressible.cpp:166

static RegImmPair getRegImmPairPreventingCompression(const MachineInstr &MI)

Definition RISCVMakeCompressible.cpp:256

This file declares the machine register scavenger class.

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

FunctionPass class - This class is used to implement most global optimizations.

bool hasMinSize() const

Optimize this function for minimum size (-Oz).

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Emit instructions to copy a pair of physical registers.

Instructions::iterator instr_iterator

LLVM_ABI StringRef getName() const

Return the name of the corresponding LLVM basic block, or an empty string.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

const MachineBasicBlock * getParent() const

MachineOperand class - Representation of each machine instruction operand.

void setImm(int64_t immVal)

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

bool hasStdExtCOrZcfOrZce() const

const RISCVInstrInfo * getInstrInfo() const override

bool hasStdExtCOrZcd() const

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

StringRef - Represent a constant reference to a string, i.e.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

FunctionPass * createRISCVMakeCompressibleOptPass()

Returns an instance of the Make Compressible Optimization pass.

Definition RISCVMakeCompressible.cpp:463

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr T maskTrailingOnes(unsigned N)

Create a bitmask with the N right-most bits set to 1, and all other bits set to 0.

constexpr bool isShiftedUInt(uint64_t x)

Checks if a unsigned integer is an N bit number shifted left by S.

Used to describe a register and immediate addition.