RISCVOptWInstrs.cpp Source File (original) (raw)

43using namespace llvm;

45#define DEBUG_TYPE "riscv-opt-w-instrs"

46#define RISCV_OPT_W_INSTRS_NAME "RISC-V Optimize W Instructions"

48 STATISTIC(NumRemovedSExtW, "Number of removed sign-extensions");

50 "Number of instructions transformed to W-ops");

52 "Number of instructions transformed to non-W-ops");

55 cl::desc("Disable removal of sext.w"),

58 cl::desc("Disable strip W suffix"),

61namespace {

64public:

65 static char ID;

69 bool runOnMachineFunction(MachineFunction &MF) override;

70 bool removeSExtWInstrs(MachineFunction &MF, const RISCVInstrInfo &TII,

71 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);

72 bool canonicalizeWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,

73 const RISCVSubtarget &ST,

74 MachineRegisterInfo &MRI);

76 void getAnalysisUsage(AnalysisUsage &AU) const override {

79 }

82};

84}

86char RISCVOptWInstrs::ID = 0;

88 false)

91 return new RISCVOptWInstrs();

92}

95 unsigned Bits) {

99 if (!MCOpcode)

100 return false;

101

105 return false;

108

110 return false;

111

112 auto NumDemandedBits =

114 return NumDemandedBits && Bits >= *NumDemandedBits;

115}

116

117

118

119

123

126

128

129 while (!Worklist.empty()) {

132 unsigned Bits = P.second;

133

134 if (!Visited.insert(P).second)

135 continue;

136

137

138 if (MI->getNumExplicitDefs() != 1)

139 return false;

140

141 Register DestReg = MI->getOperand(0).getReg();

143 return false;

144

145 for (auto &UserOp : MRI.use_nodbg_operands(DestReg)) {

147 unsigned OpIdx = UserOp.getOperandNo();

148

150 default:

152 break;

153 return false;

154

155 case RISCV::ADDIW:

156 case RISCV::ADDW:

157 case RISCV::DIVUW:

158 case RISCV::DIVW:

159 case RISCV::MULW:

160 case RISCV::REMUW:

161 case RISCV::REMW:

162 case RISCV::SLLW:

163 case RISCV::SRAIW:

164 case RISCV::SRAW:

165 case RISCV::SRLIW:

166 case RISCV::SRLW:

167 case RISCV::SUBW:

168 case RISCV::ROLW:

169 case RISCV::RORW:

170 case RISCV::RORIW:

171 case RISCV::CLZW:

172 case RISCV::CTZW:

173 case RISCV::CPOPW:

174 case RISCV::SLLI_UW:

175 case RISCV::ABSW:

176 case RISCV::FMV_W_X:

177 case RISCV::FCVT_H_W:

178 case RISCV::FCVT_H_W_INX:

179 case RISCV::FCVT_H_WU:

180 case RISCV::FCVT_H_WU_INX:

181 case RISCV::FCVT_S_W:

182 case RISCV::FCVT_S_W_INX:

183 case RISCV::FCVT_S_WU:

184 case RISCV::FCVT_S_WU_INX:

185 case RISCV::FCVT_D_W:

186 case RISCV::FCVT_D_W_INX:

187 case RISCV::FCVT_D_WU:

188 case RISCV::FCVT_D_WU_INX:

189 if (Bits >= 32)

190 break;

191 return false;

192

193 case RISCV::SEXT_B:

194 case RISCV::PACKH:

195 if (Bits >= 8)

196 break;

197 return false;

198 case RISCV::SEXT_H:

199 case RISCV::FMV_H_X:

200 case RISCV::ZEXT_H_RV32:

201 case RISCV::ZEXT_H_RV64:

202 case RISCV::PACKW:

203 if (Bits >= 16)

204 break;

205 return false;

206

207 case RISCV::PACK:

208 if (Bits >= (ST.getXLen() / 2))

209 break;

210 return false;

211

212 case RISCV::SRLI: {

213

214

215

217 if (Bits > ShAmt) {

219 break;

220 }

221 return false;

222 }

223

224

225

226 case RISCV::SLLI: {

228 if (Bits >= (ST.getXLen() - ShAmt))

229 break;

231 break;

232 }

233 case RISCV::SLLIW: {

235 if (Bits >= 32 - ShAmt)

236 break;

238 break;

239 }

240

241 case RISCV::ANDI: {

244 break;

246 break;

247 }

248 case RISCV::ORI: {

251 break;

253 break;

254 }

255

256 case RISCV::SLL:

257 case RISCV::BSET:

258 case RISCV::BCLR:

259 case RISCV::BINV:

260

261 if (OpIdx == 2) {

262 if (Bits >= Log2_32(ST.getXLen()))

263 break;

264 return false;

265 }

267 break;

268

269 case RISCV::SRA:

270 case RISCV::SRL:

271 case RISCV::ROL:

272 case RISCV::ROR:

273

274 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen()))

275 break;

276 return false;

277

278 case RISCV::ADD_UW:

279 case RISCV::SH1ADD_UW:

280 case RISCV::SH2ADD_UW:

281 case RISCV::SH3ADD_UW:

282

283 if (OpIdx == 1 && Bits >= 32)

284 break;

286 break;

287

288 case RISCV::BEXTI:

290 return false;

291 break;

292

293 case RISCV::SB:

294

295 if (OpIdx == 0 && Bits >= 8)

296 break;

297 return false;

298 case RISCV::SH:

299

300 if (OpIdx == 0 && Bits >= 16)

301 break;

302 return false;

303 case RISCV::SW:

304

305 if (OpIdx == 0 && Bits >= 32)

306 break;

307 return false;

308

309

310

311 case RISCV::COPY:

312 case RISCV::PHI:

313

314 case RISCV::ADD:

315 case RISCV::ADDI:

316 case RISCV::AND:

317 case RISCV::MUL:

318 case RISCV::OR:

319 case RISCV::SUB:

320 case RISCV::XOR:

321 case RISCV::XORI:

322

323 case RISCV::ANDN:

324 case RISCV::CLMUL:

325 case RISCV::ORN:

326 case RISCV::SH1ADD:

327 case RISCV::SH2ADD:

328 case RISCV::SH3ADD:

329 case RISCV::XNOR:

330 case RISCV::BSETI:

331 case RISCV::BCLRI:

332 case RISCV::BINVI:

334 break;

335

336 case RISCV::BREV8:

337 case RISCV::ORC_B:

338

340 break;

341

342 case RISCV::PseudoCCMOVGPR:

343 case RISCV::PseudoCCMOVGPRNoX0:

344

345

346

348 return false;

350 break;

351

352 case RISCV::CZERO_EQZ:

353 case RISCV::CZERO_NEZ:

354 case RISCV::VT_MASKC:

355 case RISCV::VT_MASKCN:

357 return false;

359 break;

360 case RISCV::TH_EXT:

361 case RISCV::TH_EXTU:

364

365 if (Msb >= Lsb && Bits > Msb)

366 break;

367 return false;

368 }

369 }

370 }

371

372 return true;

373}

374

379

380

381

383 uint64_t TSFlags = MI.getDesc().TSFlags;

384

385

387 return true;

388

389

390 switch (MI.getOpcode()) {

391

392 case RISCV::SRAI:

393 return MI.getOperand(2).getImm() >= 32;

394 case RISCV::SRLI:

395 return MI.getOperand(2).getImm() > 32;

396

397 case RISCV::ADDI:

398 return MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0;

399

400 case RISCV::ANDI:

401 return isUInt<11>(MI.getOperand(2).getImm());

402

403 case RISCV::ORI:

404 return isUInt<11> (MI.getOperand(2).getImm());

405

406 case RISCV::BSETI:

407 return MI.getOperand(2).getImm() < 31 &&

408 MI.getOperand(1).getReg() == RISCV::X0;

409

410 case RISCV::COPY:

411 return MI.getOperand(1).getReg() == RISCV::X0;

412

413 case RISCV::PseudoAtomicLoadNand32:

414 return OpNo == 0;

415 case RISCV::PseudoVMV_X_S: {

416

417 int64_t Log2SEW = MI.getOperand(2).getImm();

418 assert(Log2SEW >= 3 && Log2SEW <= 6 && "Unexpected Log2SEW");

419 return Log2SEW <= 5;

420 }

421 case RISCV::TH_EXT: {

422 unsigned Msb = MI.getOperand(2).getImm();

423 unsigned Lsb = MI.getOperand(3).getImm();

424 return Msb >= Lsb && (Msb - Lsb + 1) <= 32;

425 }

426 case RISCV::TH_EXTU: {

427 unsigned Msb = MI.getOperand(2).getImm();

428 unsigned Lsb = MI.getOperand(3).getImm();

429 return Msb >= Lsb && (Msb - Lsb + 1) < 32;

430 }

431 }

432

433 return false;

434}

435

441

442 auto AddRegToWorkList = [&](Register SrcReg) {

444 return false;

446 return true;

447 };

448

449 if (!AddRegToWorkList(SrcReg))

450 return false;

451

452 while (!Worklist.empty()) {

454

455

457 continue;

458

460 if ()

461 continue;

462

463 int OpNo = MI->findRegisterDefOperandIdx(Reg, nullptr);

464 assert(OpNo != -1 && "Couldn't find register");

465

466

468 continue;

469

470

471 switch (MI->getOpcode()) {

472 default:

473

474 return false;

475 case RISCV::COPY: {

479

480

481

482 if (MI->getParent() == &MF->front()) {

483 Register VReg = MI->getOperand(0).getReg();

485 continue;

486 }

487

488 Register CopySrcReg = MI->getOperand(1).getReg();

489 if (CopySrcReg == RISCV::X10) {

490

491

492

493

494

495

496

497

499 auto II = MI->getIterator();

500 if (II == MBB->instr_begin() ||

501 (--II)->getOpcode() != RISCV::ADJCALLSTACKUP)

502 return false;

503

506 return false;

507

508 auto *CalleeFn =

510 if (!CalleeFn)

511 return false;

512

514 if (!IntTy)

515 return false;

516

517 const AttributeSet &Attrs = CalleeFn->getAttributes().getRetAttrs();

518 unsigned BitWidth = IntTy->getBitWidth();

519 if ((BitWidth <= 32 && Attrs.hasAttribute(Attribute::SExt)) ||

520 (BitWidth < 32 && Attrs.hasAttribute(Attribute::ZExt)))

521 continue;

522 }

523

524 if (!AddRegToWorkList(CopySrcReg))

525 return false;

526

527 break;

528 }

529

530

531 case RISCV::BCLRI:

532 case RISCV::BINVI:

533 case RISCV::BSETI:

534 if (MI->getOperand(2).getImm() >= 31)

535 return false;

536 [[fallthrough]];

537 case RISCV::REM:

538 case RISCV::ANDI:

539 case RISCV::ORI:

540 case RISCV::XORI:

541 case RISCV::SRAI:

542

543

544

545

546 if (!AddRegToWorkList(MI->getOperand(1).getReg()))

547 return false;

548

549 break;

550 case RISCV::PseudoCCADDW:

551 case RISCV::PseudoCCADDIW:

552 case RISCV::PseudoCCSUBW:

553 case RISCV::PseudoCCSLLW:

554 case RISCV::PseudoCCSRLW:

555 case RISCV::PseudoCCSRAW:

556 case RISCV::PseudoCCSLLIW:

557 case RISCV::PseudoCCSRLIW:

558 case RISCV::PseudoCCSRAIW:

559

560

561 if (!AddRegToWorkList(MI->getOperand(4).getReg()))

562 return false;

563 break;

564 case RISCV::REMU:

565 case RISCV::AND:

566 case RISCV::OR:

567 case RISCV::XOR:

568 case RISCV::ANDN:

569 case RISCV::ORN:

570 case RISCV::XNOR:

571 case RISCV::MAX:

572 case RISCV::MAXU:

573 case RISCV::MIN:

574 case RISCV::MINU:

575 case RISCV::PseudoCCMOVGPR:

576 case RISCV::PseudoCCMOVGPRNoX0:

577 case RISCV::PseudoCCAND:

578 case RISCV::PseudoCCOR:

579 case RISCV::PseudoCCXOR:

580 case RISCV::PseudoCCANDN:

581 case RISCV::PseudoCCORN:

582 case RISCV::PseudoCCXNOR:

583 case RISCV::PHI: {

584

585

586

587

588

589

590

591 unsigned B = 1, E = 3, D = 1;

592 switch (MI->getOpcode()) {

593 case RISCV::PHI:

594 E = MI->getNumOperands();

595 D = 2;

596 break;

597 case RISCV::PseudoCCMOVGPR:

598 case RISCV::PseudoCCMOVGPRNoX0:

599 B = 4;

600 E = 6;

601 break;

602 case RISCV::PseudoCCAND:

603 case RISCV::PseudoCCOR:

604 case RISCV::PseudoCCXOR:

605 case RISCV::PseudoCCANDN:

606 case RISCV::PseudoCCORN:

607 case RISCV::PseudoCCXNOR:

608 B = 4;

609 E = 7;

610 break;

611 }

612

613 for (unsigned I = B; I != E; I += D) {

614 if (->getOperand(I).isReg())

615 return false;

616

617 if (!AddRegToWorkList(MI->getOperand(I).getReg()))

618 return false;

619 }

620

621 break;

622 }

623

624 case RISCV::CZERO_EQZ:

625 case RISCV::CZERO_NEZ:

626 case RISCV::VT_MASKC:

627 case RISCV::VT_MASKCN:

628

629

630 if (!AddRegToWorkList(MI->getOperand(1).getReg()))

631 return false;

632 break;

633

634 case RISCV::ADDI: {

635 if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg().isVirtual()) {

636 if (MachineInstr *SrcMI = MRI.getVRegDef(MI->getOperand(1).getReg())) {

637 if (SrcMI->getOpcode() == RISCV::LUI &&

638 SrcMI->getOperand(1).isImm()) {

639 uint64_t Imm = SrcMI->getOperand(1).getImm();

641 Imm += (uint64_t)MI->getOperand(2).getImm();

643 continue;

644 }

645 }

646 }

647

650 break;

651 }

652 return false;

653 }

654

655

656

657 case RISCV::SLLI:

658

659 if (MI->getOperand(2).getImm() >= 32)

660 return false;

661 [[fallthrough]];

662 case RISCV::ADD:

663 case RISCV::LD:

664 case RISCV::LWU:

665 case RISCV::MUL:

666 case RISCV::SUB:

669 break;

670 }

671 return false;

672 }

673 }

674

675

676

677 return true;

678}

679

680static unsigned getWOp(unsigned Opcode) {

681 switch (Opcode) {

682 case RISCV::ADDI:

683 return RISCV::ADDIW;

684 case RISCV::ADD:

685 return RISCV::ADDW;

686 case RISCV::LD:

687 case RISCV::LWU:

688 return RISCV::LW;

689 case RISCV::MUL:

690 return RISCV::MULW;

691 case RISCV::SLLI:

692 return RISCV::SLLIW;

693 case RISCV::SUB:

694 return RISCV::SUBW;

695 default:

696 llvm_unreachable("Unexpected opcode for replacement with W variant");

697 }

698}

699

700bool RISCVOptWInstrs::removeSExtWInstrs(MachineFunction &MF,

705 return false;

706

707 bool MadeChange = false;

708 for (MachineBasicBlock &MBB : MF) {

710

711 if (!RISCVInstrInfo::isSEXT_W(MI))

712 continue;

713

714 Register SrcReg = MI.getOperand(1).getReg();

715

716 SmallPtrSet<MachineInstr *, 4> FixableDefs;

717

718

719

720

723 continue;

724

725 Register DstReg = MI.getOperand(0).getReg();

726 if ( MRI .constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))

727 continue;

728

729

730 for (MachineInstr *Fixable : FixableDefs) {

732 Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));

733 Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);

734 Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);

735 Fixable->clearFlag(MachineInstr::MIFlag::IsExact);

737 ++NumTransformedToWInstrs;

738 }

739

740 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");

741 MRI.replaceRegWith(DstReg, SrcReg);

742 MRI.clearKillFlags(SrcReg);

743 MI.eraseFromParent();

744 ++NumRemovedSExtW;

745 MadeChange = true;

746 }

747 }

748

749 return MadeChange;

750}

751

752

753

754bool RISCVOptWInstrs::canonicalizeWSuffixes(MachineFunction &MF,

755 const RISCVInstrInfo &TII,

756 const RISCVSubtarget &ST,

757 MachineRegisterInfo &MRI) {

759 bool ShouldPreferW = ST.preferWInst();

760 bool MadeChange = false;

761

762 for (MachineBasicBlock &MBB : MF) {

763 for (MachineInstr &MI : MBB) {

764 std::optional WOpc;

765 std::optional NonWOpc;

766 unsigned OrigOpc = MI.getOpcode();

767 switch (OrigOpc) {

768 default:

769 continue;

770 case RISCV::ADDW:

771 NonWOpc = RISCV::ADD;

772 break;

773 case RISCV::ADDIW:

774 NonWOpc = RISCV::ADDI;

775 break;

776 case RISCV::MULW:

777 NonWOpc = RISCV::MUL;

778 break;

779 case RISCV::SLLIW:

780 NonWOpc = RISCV::SLLI;

781 break;

782 case RISCV::SUBW:

783 NonWOpc = RISCV::SUB;

784 break;

785 case RISCV::ADD:

786 WOpc = RISCV::ADDW;

787 break;

788 case RISCV::ADDI:

789 WOpc = RISCV::ADDIW;

790 break;

791 case RISCV::SUB:

792 WOpc = RISCV::SUBW;

793 break;

794 case RISCV::MUL:

795 WOpc = RISCV::MULW;

796 break;

797 case RISCV::SLLI:

798

799 if (MI.getOperand(2).getImm() >= 32)

800 continue;

801 WOpc = RISCV::SLLIW;

802 break;

803 case RISCV::LD:

804 case RISCV::LWU:

805 WOpc = RISCV::LW;

806 break;

807 }

808

809 if (ShouldStripW && NonWOpc.has_value() && hasAllWUsers(MI, ST, MRI)) {

811 MI.setDesc(TII.get(NonWOpc.value()));

813 ++NumTransformedToNonWInstrs;

814 MadeChange = true;

815 continue;

816 }

817

818

819 if ((ShouldPreferW || OrigOpc == RISCV::LWU) && WOpc.has_value() &&

822 MI.setDesc(TII.get(WOpc.value()));

823 MI.clearFlag(MachineInstr::MIFlag::NoSWrap);

824 MI.clearFlag(MachineInstr::MIFlag::NoUWrap);

825 MI.clearFlag(MachineInstr::MIFlag::IsExact);

827 ++NumTransformedToWInstrs;

828 MadeChange = true;

829 continue;

830 }

831 }

832 }

833 return MadeChange;

834}

835

836bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {

838 return false;

839

841 const RISCVSubtarget &ST = MF.getSubtarget();

842 const RISCVInstrInfo &TII = *ST.getInstrInfo();

843

844 if (.is64Bit())

845 return false;

846

847 bool MadeChange = false;

848 MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI);

849 MadeChange |= canonicalizeWSuffixes(MF, TII, ST, MRI);

850 return MadeChange;

851}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

const HexagonInstrInfo * TII

static cl::opt< bool > DisableSExtWRemoval("loongarch-disable-sextw-removal", cl::desc("Disable removal of sign-extend insn"), cl::init(false), cl::Hidden)

static bool hasAllWUsers(const MachineInstr &OrigMI, const LoongArchSubtarget &ST, const MachineRegisterInfo &MRI)

static bool isSignExtendedW(Register SrcReg, const LoongArchSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)

static unsigned getWOp(unsigned Opcode)

Promote Memory to Register

MachineInstr unsigned OpIdx

uint64_t IntrinsicInst * II

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)

Definition RISCVOptWInstrs.cpp:436

static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI)

Definition RISCVOptWInstrs.cpp:375

static bool isSignExtendingOpW(const MachineInstr &MI, unsigned OpNo)

Definition RISCVOptWInstrs.cpp:382

static cl::opt< bool > DisableStripWSuffix("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden)

static bool hasAllNBitUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits)

Definition RISCVOptWInstrs.cpp:120

#define RISCV_OPT_W_INSTRS_NAME

Definition RISCVOptWInstrs.cpp:46

static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp, unsigned Bits)

Definition RISCVOptWInstrs.cpp:94

static cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)

static unsigned getWOp(unsigned Opcode)

Definition RISCVOptWInstrs.cpp:680

This file defines the SmallSet class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

This class holds the attributes for a particular argument, parameter, function, or return value.

FunctionPass class - This class is used to implement most global optimizations.

Describe properties that are true of each instruction in the target description file.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineBasicBlock & front() const

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

const MachineBasicBlock * getParent() const

bool isCall(QueryType Type=AnyInBundle) const

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

LLVM_ABI unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

const GlobalValue * getGlobal() const

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

bool isGlobal() const

isGlobal - Tests if this is a MO_GlobalAddress operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI bool isLiveIn(Register Reg) const

RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...

bool isSExt32Register(Register Reg) const

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

reference emplace_back(ArgTypes &&... Args)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

static unsigned getVLOpNum(const MCInstrDesc &Desc)

static bool hasVLOp(uint64_t TSFlags)

static unsigned getSEWOpNum(const MCInstrDesc &Desc)

static bool hasSEWOp(uint64_t TSFlags)

unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)

std::optional< unsigned > getVectorLowDemandedScalarBits(unsigned Opcode, unsigned Log2SEW)

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

auto dyn_cast_if_present(const Y &Val)

dyn_cast_if_present - Functionally identical to dyn_cast, except that a null (or none in the case ...

int bit_width(T Value)

Returns the number of bits needed to represent Value if Value is nonzero.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

constexpr T alignDown(U Value, V Align, W Skew=0)

Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.

unsigned Log2_32(uint32_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

FunctionPass * createRISCVOptWInstrsPass()

constexpr unsigned BitWidth

constexpr int64_t SignExtend64(uint64_t x)

Sign-extend the number in the bottom B bits of X to a 64-bit integer.