RegisterBankInfo.cpp Source File (original) (raw)

23#include "llvm/Config/llvm-config.h"

27#include

29#define DEBUG_TYPE "registerbankinfo"

31using namespace llvm;

34 "Number of partial mappings dynamically created");

36 "Number of partial mappings dynamically accessed");

38 "Number of value mappings dynamically created");

40 "Number of value mappings dynamically accessed");

42 "Number of operands mappings dynamically created");

44 "Number of operands mappings dynamically accessed");

46 "Number of instruction mappings dynamically created");

48 "Number of instruction mappings dynamically accessed");

61#ifndef NDEBUG

62 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {

63 assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");

65 "RegisterBank ID should match index");

66 }

67#endif

68}

71#ifndef NDEBUG

72 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {

75 "ID does not match the index in the array");

77 assert(RegBank.verify(*this, TRI) && "RegBank is invalid");

78 }

79#endif

80 return true;

81}

86 if (!Reg.isVirtual()) {

91 }

95 return RB;

96 if (auto *RC =

99 return nullptr;

100}

101

105 const auto [RegRCIt, Inserted] = PhysRegMinimalRCs.try_emplace(Reg);

106 if (Inserted)

107 RegRCIt->second = TRI.getMinimalPhysRegClassLLT(Reg, LLT());

108 return RegRCIt->second;

109}

110

115

116

117

119

120 if (!RC)

121 return nullptr;

122

125

127 "The mapping of the register bank does not make sense");

128 return &RegBank;

129}

130

133

134

135 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);

137 return MRI.constrainRegClass(Reg, &RC);

138

140

141 if (RB && !RB->covers(RC))

142 return nullptr;

143

144

145 MRI.setRegClass(Reg, &RC);

146 return &RC;

147}

148

149

150

151

152

153

154

156 return MI.isCopy() || MI.isPHI() ||

157 MI.getOpcode() == TargetOpcode::REG_SEQUENCE;

158}

159

162

163

164

166

167

168 unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();

169

174

176

177

178

179 bool CompleteMapping = true;

180

182 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;

186 continue;

188 if (!Reg)

189 continue;

190

191

192

193

194

196

197

198

199 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;

200 if (!CurRegBank) {

201

202

204 if (!CurRegBank) {

205

206 CompleteMapping = false;

207

208 if (!IsCopyLike)

209

211 continue;

212 }

213 }

214

218 if (IsCopyLike) {

219 if (!OperandsMapping[0]) {

220 if (MI.isRegSequence()) {

221

222 unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),

224 OperandsMapping[0] = &getValueMapping(0, ResultSize, *CurRegBank);

225 } else {

226 OperandsMapping[0] = ValMapping;

227 }

228 }

229

230

231

232

236 continue;

238 if (!Reg)

239 continue;

240

242 if (AltRegBank &&

245 }

246

247 CompleteMapping = true;

248 break;

249 }

250

251 OperandsMapping[OpIdx] = ValMapping;

252 }

253

254 if (IsCopyLike && !CompleteMapping) {

255

257 }

258

259 assert(CompleteMapping && "Setting an uncomplete mapping");

263 NumOperandsForMapping);

264}

265

266

271

272

278

282 ++NumPartialMappingsAccessed;

283

286 if (!Inserted)

287 return *It->second;

288

289 ++NumPartialMappingsCreated;

290

291 auto &PartMapping = It->second;

292 PartMapping = std::make_unique(StartIdx, Length, RegBank);

293 return *PartMapping;

294}

295

301

304 unsigned NumBreakDowns) {

308 for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)

311}

312

315 unsigned NumBreakDowns) const {

316 ++NumValueMappingsAccessed;

317

320 if (!Inserted)

321 return *It->second;

322

323 ++NumValueMappingsCreated;

324

325 auto &ValMapping = It->second;

326 ValMapping = std::make_unique(BreakDown, NumBreakDowns);

327 return *ValMapping;

328}

329

330template

333

334 ++NumOperandsMappingsAccessed;

335

336

337

340 if (Res)

341 return Res.get();

342

343 ++NumOperandsMappingsCreated;

344

345

346

347

348

349

350 Res = std::make_unique<ValueMapping[]>(std::distance(Begin, End));

351 unsigned Idx = 0;

352 for (Iterator It = Begin; It != End; ++It, ++Idx) {

354 if (!ValMap)

355 continue;

356 Res[Idx] = *ValMap;

357 }

358 return Res.get();

359}

360

366

368 std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)

369 const {

371}

372

376 unsigned NumOperands) {

377 return hash_combine(ID, Cost, OperandsMapping, NumOperands);

378}

379

381RegisterBankInfo::getInstructionMappingImpl(

382 bool IsInvalid, unsigned ID, unsigned Cost,

384 unsigned NumOperands) const {

386 OperandsMapping == nullptr && NumOperands == 0) ||

387 !IsInvalid) &&

388 "Mismatch argument for invalid input");

389 ++NumInstructionMappingsAccessed;

390

391 hash_code Hash =

394 if (!Inserted)

395 return *It->second;

396

397 ++NumInstructionMappingsCreated;

398

399 auto &InstrMapping = It->second;

400 InstrMapping = std::make_unique(

401 ID, Cost, OperandsMapping, NumOperands);

402 return *InstrMapping;

403}

404

412

417 if (Mapping.isValid()) {

418

419 PossibleMappings.push_back(&Mapping);

420 }

421

422

425#ifndef NDEBUG

427 assert(Mapping->verify(MI) && "Mapping is invalid");

428#endif

429 return PossibleMappings;

430}

431

437

441 LLVM_DEBUG(dbgs() << "Applying default-like mapping\n");

442 for (unsigned OpIdx = 0,

447 if (!MO.isReg()) {

448 LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n");

449 continue;

450 }

452 LLVM_DEBUG(dbgs() << " is $noreg, nothing to be done\n");

453 continue;

454 }

456 if (!Ty.isValid())

457 continue;

459 0 &&

460 "Invalid mapping");

462 1 &&

463 "This mapping is too complex for this function");

466 if (NewRegs.empty()) {

467 LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n");

468 continue;

469 }

475

476

477

478 LLT OrigTy = MRI.getType(OrigReg);

479 LLT NewTy = MRI.getType(NewReg);

480 if (OrigTy != NewTy) {

481

482

483

484

487 "Types with difference size cannot be handled by the default "

488 "mapping");

489 LLVM_DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "

490 << OrigTy);

491 MRI.setType(NewReg, OrigTy);

492 }

494 }

495}

496

500 if (Reg.isPhysical()) {

501

502

503

504

506 assert(RC && "Expecting Register class");

507 return TRI.getRegSizeInBits(*RC);

508 }

509 return TRI.getRegSizeInBits(Reg, MRI);

510}

511

512

513

514

515#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

520#endif

521

527

529 "Register bank too small for Mask");

530 return true;

531}

532

537 else

538 OS << "nullptr";

539}

540

543 return true;

544

547 if (Part->Length != First->Length || Part->RegBank != First->RegBank)

548 return false;

549 }

550

551 return true;

552}

553

555 TypeSize MeaningfulBitWidth) const {

557 unsigned OrigValueBitWidth = 0;

559

560

561 assert(PartMap.verify(RBI) && "Partial mapping is invalid");

562

563

564 OrigValueBitWidth =

565 std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);

566 }

568 OrigValueBitWidth >= MeaningfulBitWidth) &&

569 "Meaningful bits not covered by the mapping");

570 APInt ValueMask(OrigValueBitWidth, 0);

572

573

574

577 ValueMask ^= PartMapMask;

578 assert((ValueMask & PartMapMask) == PartMapMask &&

579 "Some partial mappings overlap");

580 }

581 assert(ValueMask.isAllOnes() && "Value is not fully mapped");

582 return true;

583}

584

585#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

590#endif

591

594 bool IsFirst = true;

596 if (!IsFirst)

597 OS << ", ";

598 OS << '[' << PartMap << ']';

599 IsFirst = false;

600 }

601}

602

605

606

607

609 "NumOperands must match, see constructor");

610 assert(MI.getParent() && MI.getMF() &&

611 "MI must be connected to a MachineFunction");

614 (void)RBI;

616

617 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {

619 if (!MO.isReg()) {

621 "We should not care about non-reg mapping");

622 continue;

623 }

625 if (!Reg)

626 continue;

627 LLT Ty = MRI.getType(Reg);

628 if (!Ty.isValid())

629 continue;

631 "We must have a mapping for reg operands");

633 (void)MOMapping;

634

635

639 "Value mapping is invalid");

640 }

641 return true;

642}

643

644#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

649#endif

650

652 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";

653

654 for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {

657 OS << ", ";

658 OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';

659 }

660}

661

662const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;

663

667 : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {

668 unsigned NumOpds = InstrMapping.getNumOperands();

669 OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);

670 assert(InstrMapping.verify(MI) && "Invalid mapping for MI");

671}

672

674RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {

676 unsigned NumPartialVal =

678 int StartIdx = OpToNewVRegIdx[OpIdx];

679

680 if (StartIdx == OperandsMapper::DontKnowIdx) {

681

682

683

684 StartIdx = NewVRegs.size();

685 OpToNewVRegIdx[OpIdx] = StartIdx;

686 for (unsigned i = 0; i < NumPartialVal; ++i)

687 NewVRegs.push_back(0);

688 }

690 getNewVRegsEnd(StartIdx, NumPartialVal);

691

692 return make_range(&NewVRegs[StartIdx], End);

693}

694

696RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,

697 unsigned NumVal) const {

698 return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);

699}

701RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,

702 unsigned NumVal) {

703 assert((NewVRegs.size() == StartIdx + NumVal ||

704 NewVRegs.size() > StartIdx + NumVal) &&

705 "NewVRegs too small to contain all the partial mapping");

706 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()

707 : &NewVRegs[StartIdx + NumVal];

708}

709

713 getVRegsMem(OpIdx);

716 for (Register &NewVReg : NewVRegsForOpIdx) {

717 assert(PartMap != ValMapping.end() && "Out-of-bound access");

718 assert(NewVReg == 0 && "Register has already been created");

719

720

721

722

723

724 NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));

725 MRI.setRegBank(NewVReg, *PartMap->RegBank);

726 ++PartMap;

727 }

728}

729

731 unsigned PartialMapIdx,

735 PartialMapIdx &&

736 "Out-of-bound access for partial mapping");

737

738 (void)getVRegsMem(OpIdx);

739 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&

740 "This value is already set");

741 NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;

742}

743

746 bool ForDebug) const {

747 (void)ForDebug;

749 int StartIdx = OpToNewVRegIdx[OpIdx];

750

751 if (StartIdx == OperandsMapper::DontKnowIdx)

752 return make_range(NewVRegs.end(), NewVRegs.end());

753

754 unsigned PartMapSize =

757 getNewVRegsEnd(StartIdx, PartMapSize);

759 make_range(&NewVRegs[StartIdx], End);

760#ifndef NDEBUG

762 assert((VReg || ForDebug) && "Some registers are uninitialized");

763#endif

764 return Res;

765}

766

767#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

772#endif

773

775 bool ForDebug) const {

777 if (ForDebug) {

779

780 OS << "Populated indices (CellNumber, IndexInNewVRegs): ";

781 bool IsFirst = true;

782 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {

783 if (OpToNewVRegIdx[Idx] != DontKnowIdx) {

784 if (!IsFirst)

785 OS << ", ";

786 OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';

787 IsFirst = false;

788 }

789 }

790 OS << '\n';

791 } else

793

794 OS << "Operand Mapping: ";

795

796

798 getMI().getParent() && getMI().getMF()

799 ? getMI().getMF()->getSubtarget().getRegisterInfo()

800 : nullptr;

801 bool IsFirst = true;

802 for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {

803 if (OpToNewVRegIdx[Idx] == DontKnowIdx)

804 continue;

805 if (!IsFirst)

806 OS << ", ";

807 IsFirst = false;

809 bool IsFirstNewVReg = true;

811 if (!IsFirstNewVReg)

812 OS << ", ";

813 IsFirstNewVReg = false;

815 }

816 OS << "])";

817 }

818}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file implements a class to represent arbitrary precision integral constant values and operations...

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

#define LLVM_LIKELY(EXPR)

static InstructionCost getCost(Instruction &Inst, TTI::TargetCostKind CostKind, TargetTransformInfo &TTI, TargetLibraryInfo &TLI)

const HexagonInstrInfo * TII

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

MachineInstr unsigned OpIdx

static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)

Hashing function for PartialMapping.

Definition RegisterBankInfo.cpp:267

static bool isCopyLike(const MachineInstr &MI)

Check whether or not MI should be treated like a copy for the mappings.

Definition RegisterBankInfo.cpp:155

static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)

Definition RegisterBankInfo.cpp:303

static hash_code hashInstructionMapping(unsigned ID, unsigned Cost, const RegisterBankInfo::ValueMapping *OperandsMapping, unsigned NumOperands)

Definition RegisterBankInfo.cpp:374

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

Class for arbitrary precision integers.

bool isAllOnes() const

Determine if all bits are set. This is true for zero-width values.

static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)

Get a value with a block of bits set.

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

Wrapper class representing physical registers. Should be passed by value.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Helper class that represents how the value of an instruction may be mapped and what is the related co...

unsigned getNumOperands() const

Get the number of operands.

unsigned getID() const

Get the ID.

bool verify(const MachineInstr &MI) const

Verifiy that this mapping makes sense for MI.

Definition RegisterBankInfo.cpp:603

void dump() const

Print this on dbgs() stream.

Definition RegisterBankInfo.cpp:645

void print(raw_ostream &OS) const

Print this on OS;.

Definition RegisterBankInfo.cpp:651

bool isValid() const

Check whether this object is valid.

Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...

const InstructionMapping & getInstrMapping() const

The final mapping of the instruction.

void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)

Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg.

Definition RegisterBankInfo.cpp:730

void print(raw_ostream &OS, bool ForDebug=false) const

Print this operands mapper on OS stream.

Definition RegisterBankInfo.cpp:774

MachineInstr & getMI() const

void createVRegs(unsigned OpIdx)

Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.

Definition RegisterBankInfo.cpp:710

MachineRegisterInfo & getMRI() const

The MachineRegisterInfo we used to realize the mapping.

OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)

Create an OperandsMapper that will hold the information to apply InstrMapping to MI.

Definition RegisterBankInfo.cpp:664

void dump() const

Print this operands mapper on dbgs() stream.

Definition RegisterBankInfo.cpp:768

iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const

Get all the virtual registers required to map the OpIdx-th operand of the instruction.

Definition RegisterBankInfo.cpp:745

const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const

Get the uniquely generated PartialMapping for the given arguments.

Definition RegisterBankInfo.cpp:280

virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const

Get the alternative mappings for MI.

Definition RegisterBankInfo.cpp:433

static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)

Constrain the (possibly generic) virtual register Reg to RC.

Definition RegisterBankInfo.cpp:131

DenseMap< hash_code, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings

Keep dynamically allocated InstructionMapping in a separate map.

const RegisterBank ** RegBanks

Hold the set of supported register banks.

RegisterBankInfo()

This constructor is meaningless.

DenseMap< hash_code, std::unique_ptr< const PartialMapping > > MapOfPartialMappings

Keep dynamically allocated PartialMapping in a separate map.

virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const

Get the mapping of the different operands of MI on the register bank.

Definition RegisterBankInfo.cpp:406

unsigned NumRegBanks

Total number of register banks.

const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const

Method to get a uniquely generated InstructionMapping.

static void applyDefaultMapping(const OperandsMapper &OpdMapper)

Helper method to apply something that is like the default mapping.

Definition RegisterBankInfo.cpp:438

DenseMap< hash_code, std::unique_ptr< const ValueMapping > > MapOfValueMappings

Keep dynamically allocated ValueMapping in a separate map.

const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const

The most common ValueMapping consists of a single PartialMapping.

Definition RegisterBankInfo.cpp:297

const InstructionMapping & getInvalidInstructionMapping() const

Method to get a uniquely generated invalid InstructionMapping.

DenseMap< hash_code, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings

Keep dynamically allocated array of ValueMapping in a separate map.

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

const unsigned * Sizes

Hold the sizes of the register banks for all HwModes.

bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const

unsigned getMaximumSize(unsigned RegBankID) const

Get the maximum size in bits that fits in the given register bank.

unsigned getNumRegBanks() const

Get the total number of register banks.

const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const

Get the register bank for the OpIdx-th operand of MI form the encoding constraints,...

Definition RegisterBankInfo.cpp:111

TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const

Get the size in bits of Reg.

Definition RegisterBankInfo.cpp:497

virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const

Get a register bank that covers RC.

InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const

Get the possible mapping for MI.

Definition RegisterBankInfo.cpp:414

RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode)

Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.

Definition RegisterBankInfo.cpp:56

static const unsigned InvalidMappingID

Identifier used when the related instruction mapping instance is generated by the default constructor...

const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, const TargetRegisterInfo &TRI) const

Get the MinimalPhysRegClass for Reg.

Definition RegisterBankInfo.cpp:103

const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

Definition RegisterBankInfo.cpp:332

DenseMap< MCRegister, const TargetRegisterClass * > PhysRegMinimalRCs

Getting the minimal register class of a physreg is expensive.

static const unsigned DefaultMappingID

Identifier used when the related instruction mapping instance is generated by target independent code...

unsigned HwMode

Current HwMode for the target.

SmallVector< const InstructionMapping *, 4 > InstructionMappings

Convenient type to represent the alternatives for mapping an instruction.

bool verify(const TargetRegisterInfo &TRI) const

Check that information hold by this instance make sense for the given TRI.

Definition RegisterBankInfo.cpp:70

const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const

Try to get the mapping of MI.

Definition RegisterBankInfo.cpp:161

This class implements the register bank concept.

LLVM_ABI bool verify(const RegisterBankInfo &RBI, const TargetRegisterInfo &TRI) const

Check if this register bank is valid.

LLVM_ABI bool covers(const TargetRegisterClass &RC) const

Check whether this register bank covers RC.

unsigned getID() const

Get the identifier of this register bank.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

typename SuperClass::const_iterator const_iterator

typename SuperClass::iterator iterator

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual const RegisterBankInfo * getRegBankInfo() const

If the information for the register banks is available, return it.

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

static constexpr bool isKnownLE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)

constexpr bool isScalable() const

Returns whether the quantity is scaled by a runtime quantity (vscale).

An opaque object representing a hash code.

A range adaptor for a pair of iterators.

This class implements an extremely fast bulk output stream that can only output to a stream.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

hash_code hash_value(const FixedPointSemantics &Val)

PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank

Convenient type to represent either a register class or a register bank.

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

auto dyn_cast_if_present(const Y &Val)

dyn_cast_if_present - Functionally identical to dyn_cast, except that a null (or none in the case ...

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

void append_range(Container &C, Range &&R)

Wrapper function to append range R to container C.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

hash_code hash_combine(const Ts &...args)

Combine values into a single hash_code.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)

Compute a hash_code for a sequence of values.

Helper struct that represents how a value is partially mapped into a register.

void print(raw_ostream &OS) const

Print this partial mapping on OS;.

Definition RegisterBankInfo.cpp:533

unsigned StartIdx

Number of bits at which this partial mapping starts in the original value.

unsigned getHighBitIdx() const

bool verify(const RegisterBankInfo &RBI) const

Check that the Mask is compatible with the RegBank.

Definition RegisterBankInfo.cpp:522

void dump() const

Print this partial mapping on dbgs() stream.

Definition RegisterBankInfo.cpp:516

const RegisterBank * RegBank

unsigned Length

Length of this mapping in bits.

Helper struct that represents how a value is mapped through different register banks.

const PartialMapping * begin() const

Iterators through the PartialMappings.

const PartialMapping * end() const

void print(raw_ostream &OS) const

Print this on OS;.

Definition RegisterBankInfo.cpp:592

bool verify(const RegisterBankInfo &RBI, TypeSize MeaningfulBitWidth) const

Verify that this mapping makes sense for a value of MeaningfulBitWidth.

Definition RegisterBankInfo.cpp:554

bool partsAllUniform() const

Definition RegisterBankInfo.cpp:541

unsigned NumBreakDowns

Number of partial mapping to break down this value.

void dump() const

Print this on dbgs() stream.

Definition RegisterBankInfo.cpp:586