RemoveLoadsIntoFakeUses.cpp Source File (original) (raw)

36using namespace llvm;

38#define DEBUG_TYPE "remove-loads-into-fake-uses"

40 STATISTIC(NumLoadsDeleted, "Number of dead load instructions deleted");

41 STATISTIC(NumFakeUsesDeleted, "Number of FAKE_USE instructions deleted");

44public:

45 static char ID;

49 }

54 }

58 MachineFunctionProperties::Property::NoVRegs);

59 }

62 return "Remove Loads Into Fake Uses";

63 }

66};

72 "Remove Loads Into Fake Uses", false, false)

78 if (!MF.hasFakeUses() || skipFunction(MF.getFunction()))

79 return false;

81 bool AnyChanges = false;

96 if (MI.isFakeUse()) {

100 if (MO.isReg())

101 RegFakeUses[MO.getReg()].push_back(&MI);

102 }

103

104

105 continue;

106 }

107

108

109

110 if (MI.getRestoreSize(TII)) {

111 Register Reg = MI.getOperand(0).getReg();

112 assert(Reg.isPhysical() && "VReg seen in function with NoVRegs set?");

113

115 continue;

116

117

118

119 if (RegFakeUses.contains(Reg)) {

120 LLVM_DEBUG(dbgs() << "RemoveLoadsIntoFakeUses: DELETING: " << MI);

121

122

123

124 MI.eraseFromParent();

125 AnyChanges = true;

126 ++NumLoadsDeleted;

127

128

129

130 for (MachineInstr *FakeUse : RegFakeUses[Reg]) {

132 << "RemoveLoadsIntoFakeUses: DELETING: " << *FakeUse);

133 FakeUse->eraseFromParent();

134 }

135 NumFakeUsesDeleted += RegFakeUses[Reg].size();

136 RegFakeUses[Reg].clear();

137 }

138 continue;

139 }

140

141

142

143

144 if (!RegFakeUses.empty()) {

146 if (MO.isReg() && MO.isDef()) {

148 assert(Reg.isPhysical() &&

149 "VReg seen in function with NoVRegs set?");

151 RegFakeUses.erase(Unit);

152 }

153 }

154 }

156 }

157 }

158

159 return AnyChanges;

160}

unsigned const MachineRegisterInfo * MRI

const HexagonInstrInfo * TII

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.

Remove Loads Into Fake Uses

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

bool runOnMachineFunction(MachineFunction &MF) override

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

MachineFunctionProperties getRequiredProperties() const override

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

RemoveLoadsIntoFakeUses()

StringRef getPassName() const override

getPassName - Return a nice clean name for a pass.

Represent the analysis usage information of a pass.

void setPreservesCFG()

This function should be called by the pass, iff they do not:

bool erase(const KeyT &Val)

bool contains(const_arg_type_t< KeyT > Val) const

Return true if the specified key is in the map, false otherwise.

A set of physical registers with utility functions to track liveness when walking backward/forward th...

bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const

Returns true if register Reg and no aliasing register is in the set.

void stepBackward(const MachineInstr &MI)

Simulates liveness when stepping backwards over an instruction(bundle).

void init(const TargetRegisterInfo &TRI)

(re-)initializes and clears the set.

void addLiveOuts(const MachineBasicBlock &MBB)

Adds all live-out registers of basic block MBB.

A set of register units used to track register liveness.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Properties which a MachineFunction may have at a given point in time.

MachineFunctionProperties & set(Property P)

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Wrapper class representing virtual and physical registers.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This is an optimization pass for GlobalISel generic memory operations.

iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)

Make a range that does early increment to allow mutation of the underlying range without disrupting i...

char & RemoveLoadsIntoFakeUsesID

RemoveLoadsIntoFakeUses pass.

iterator_range< po_iterator< T > > post_order(const T &G)

void initializeRemoveLoadsIntoFakeUsesPass(PassRegistry &)

auto reverse(ContainerTy &&C)

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.