SIProgramInfo.cpp Source File (original) (raw)

23using namespace llvm;

80}

92 if (ST.hasDX10ClampMode())

95 if (ST.hasIEEEMode())

98 if (ST.hasRrWGMode())

100

101 return Reg;

102}

103

110

111 if (ST.hasDX10ClampMode())

113

114 if (ST.hasIEEEMode())

116

117 if (ST.hasRrWGMode())

119

120 switch (CC) {

123 break;

126 break;

130 break;

134 break;

135 default:

136 break;

137 }

138 return Reg;

139}

140

155

158 if (Mask) {

161 }

162 if (Shift) {

165 }

166 return Val;

167}

168

178

193

199

207

209 bool IsLowerBound) {

212

215

217

219

220

221

222

223 if (!IsLowerBound)

225

227

228

229 if (MI.isMetaInstruction())

230 continue;

231

232

233

234 if (IsLowerBound && MI.isInlineAsm())

235 continue;

236

238 }

239 }

240

243}

AMD GCN specific subclass of TargetSubtarget.

const HexagonInstrInfo * TII

#define S_00B84C_EXCP_EN(x)

#define S_00B428_MEM_ORDERED(x)

#define S_00B028_MEM_ORDERED(x)

#define S_00B84C_TGID_Z_EN(x)

#define S_00B228_WGP_MODE(x)

#define S_00B848_MEM_ORDERED(x)

#define S_00B228_MEM_ORDERED(x)

#define S_00B848_RR_WG_MODE(x)

#define S_00B84C_TGID_X_EN(x)

#define S_00B848_DEBUG_MODE(x)

#define S_00B428_WGP_MODE(x)

#define S_00B84C_TG_SIZE_EN(x)

#define S_00B84C_TIDIG_COMP_CNT(x)

#define S_00B84C_LDS_SIZE(x)

#define S_00B84C_USER_SGPR(x)

#define S_00B84C_TRAP_HANDLER(x)

#define S_00B84C_TGID_Y_EN(x)

#define S_00B128_MEM_ORDERED(x)

#define S_00B848_WGP_MODE(x)

#define S_00B84C_EXCP_EN_MSB(x)

#define S_00B848_DX10_CLAMP(x)

#define S_00B848_PRIORITY(x)

#define S_00B848_IEEE_MODE(x)

#define S_00B848_FWD_PROGRESS(x)

#define S_00B848_FLOAT_MODE(x)

static uint64_t getComputePGMRSrc2Reg(const SIProgramInfo &ProgInfo)

Definition SIProgramInfo.cpp:141

static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo, CallingConv::ID CC, const GCNSubtarget &ST)

Definition SIProgramInfo.cpp:104

static uint64_t getComputePGMRSrc1Reg(const SIProgramInfo &ProgInfo, const GCNSubtarget &ST)

Definition SIProgramInfo.cpp:82

static const MCExpr * MaskShift(const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)

Definition SIProgramInfo.cpp:156

Defines struct to track resource usage and hardware flags for kernels and entry functions.

const SIInstrInfo * getInstrInfo() const override

static const MCBinaryExpr * createAnd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static const MCBinaryExpr * createOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static const MCBinaryExpr * createShl(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MCContext & getContext() const

Representation of each machine instruction.

LLVM_READNONE constexpr bool isCompute(CallingConv::ID CC)

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ AMDGPU_VS

Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...

@ AMDGPU_HS

Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).

@ AMDGPU_GS

Used for Mesa/AMDPAL geometry shaders.

@ AMDGPU_PS

Used for Mesa/AMDPAL pixel shaders.

This is an optimization pass for GlobalISel generic memory operations.

uint64_t alignTo(uint64_t Size, Align A)

Returns a multiple of A needed to store Size bytes.

Track resource usage for kernels / entry functions.

const MCExpr * getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const

Definition SIProgramInfo.cpp:200

const MCExpr * NumArchVGPR

uint64_t getFunctionCodeSize(const MachineFunction &MF, bool IsLowerBound=false)

Definition SIProgramInfo.cpp:208

const MCExpr * getComputePGMRSrc2(MCContext &Ctx) const

Compute the value of the ComputePGMRsrc2 register.

Definition SIProgramInfo.cpp:194

const MCExpr * VGPRBlocks

const MCExpr * ScratchBlocks

const MCExpr * ComputePGMRSrc3

const MCExpr * getComputePGMRSrc1(const GCNSubtarget &ST, MCContext &Ctx) const

Compute the value of the ComputePGMRsrc1 register.

Definition SIProgramInfo.cpp:169

uint32_t TrapHandlerEnable

const MCExpr * NamedBarCnt

const MCExpr * ScratchEnable

const MCExpr * AccumOffset

const MCExpr * NumAccVGPR

const MCExpr * DynamicCallStack

const MCExpr * SGPRBlocks

const MCExpr * NumVGPRsForWavesPerEU

std::optional< uint64_t > CodeSizeInBytes

const MCExpr * getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST, MCContext &Ctx) const

Definition SIProgramInfo.cpp:179

const MCExpr * ScratchSize

const MCExpr * NumSGPRsForWavesPerEU

void reset(const MachineFunction &MF)

Definition SIProgramInfo.cpp:25