LLVM: lib/Target/SPIRV/SPIRVLegalizerInfo.cpp Source File (original) (raw)

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23#include "llvm/IR/IntrinsicsSPIRV.h"

26

27using namespace llvm;

30

31#define DEBUG_TYPE "spirv-legalizer"

32

34 return [IsExtendedInts, TypeIdx](const LegalityQuery &Query) {

35 const LLT Ty = Query.Types[TypeIdx];

36 return IsExtendedInts && Ty.isValid() && Ty.isScalar();

37 };

38}

39

42

43 this->ST = &ST;

45

52

58

64

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76

82

83 const unsigned PSize = ST.getPointerSize();

89 const LLT p5 =

90 LLT::pointer(5, PSize);

91 const LLT p6 = LLT::pointer(6, PSize);

94 const LLT p9 =

95 LLT::pointer(9, PSize);

99

100

101 auto allPtrsScalarsAndVectors = {

102 p0, p1, p2, p3, p4, p5, p6, p7, p8,

103 p9, p10, p11, p12, s1, s8, s16, s32, s64,

104 v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8, v3s16, v3s32,

105 v3s64, v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,

106 v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};

107

108 auto allVectors = {v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,

109 v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32,

110 v4s64, v8s1, v8s8, v8s16, v8s32, v8s64, v16s1,

111 v16s8, v16s16, v16s32, v16s64};

112

113 auto allShaderVectors = {v2s1, v2s8, v2s16, v2s32, v2s64,

114 v3s1, v3s8, v3s16, v3s32, v3s64,

115 v4s1, v4s8, v4s16, v4s32, v4s64};

116

117 auto allScalarsAndVectors = {

118 s1, s8, s16, s32, s64, s128, v2s1, v2s8,

119 v2s16, v2s32, v2s64, v3s1, v3s8, v3s16, v3s32, v3s64,

120 v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,

121 v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};

122

123 auto allIntScalarsAndVectors = {

124 s8, s16, s32, s64, s128, v2s8, v2s16, v2s32, v2s64,

125 v3s8, v3s16, v3s32, v3s64, v4s8, v4s16, v4s32, v4s64, v8s8,

126 v8s16, v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};

127

128 auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};

129

130 auto allIntScalars = {s8, s16, s32, s64, s128};

131

132 auto allFloatScalarsAndF16Vector2AndVector4s = {s16, s32, s64, v2s16, v4s16};

133

134 auto allFloatScalarsAndVectors = {

135 s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,

136 v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};

137

138 auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0, p1, p2, p3, p4,

139 p5, p6, p7, p8, p9, p10, p11, p12};

140

141 auto allPtrs = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12};

142

143 auto &allowedVectorTypes = ST.isShader() ? allShaderVectors : allVectors;

144

145 bool IsExtendedInts =

146 ST.canUseExtension(

147 SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||

148 ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||

149 ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4);

150 auto extendedScalarsAndVectors =

152 const LLT Ty = Query.Types[0];

153 return IsExtendedInts && Ty.isValid() && !Ty.isPointerOrPointerVector();

154 };

155 auto extendedScalarsAndVectorsProduct = [IsExtendedInts](

157 const LLT Ty1 = Query.Types[0], Ty2 = Query.Types[1];

158 return IsExtendedInts && Ty1.isValid() && Ty2.isValid() &&

160 };

161 auto extendedPtrsScalarsAndVectors =

163 const LLT Ty = Query.Types[0];

164 return IsExtendedInts && Ty.isValid();

165 };

166

167

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169

170

171

172

173 uint32_t MaxVectorSize = ST.isShader() ? 4 : 16;

174

176 if (Opc != G_EXTRACT_VECTOR_ELT)

178 }

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233

235 {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,

236 G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,

237 G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,

238 G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})

239 .legalFor(allowedVectorTypes)

242

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251

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259

265

267 .unsupportedIf(typeIs(1, p9))

269

271 G_BITREVERSE, G_SADDSAT, G_UADDSAT, G_SSUBSAT,

272 G_USUBSAT, G_SCMP, G_UCMP})

273 .legalFor(allIntScalarsAndVectors)

274 .legalIf(extendedScalarsAndVectors);

275

277 .legalFor(allFloatScalarsAndVectors);

278

281

283 .legalForCartesianProduct(allIntScalarsAndVectors,

284 allFloatScalarsAndVectors);

285

287 .legalForCartesianProduct(allIntScalarsAndVectors,

288 allFloatScalarsAndVectors);

289

291 .legalForCartesianProduct(allFloatScalarsAndVectors,

292 allScalarsAndVectors);

293

296 .legalIf(extendedScalarsAndVectorsProduct);

297

298

300 .legalForCartesianProduct(allScalarsAndVectors)

301 .legalIf(extendedScalarsAndVectorsProduct);

302

304 .legalFor(allPtrsScalarsAndVectors)

305 .legalIf(extendedPtrsScalarsAndVectors);

306

309 typeInSet(1, allPtrsScalarsAndVectors)));

310

312 .legalFor({s1, s128})

313 .legalFor(allFloatAndIntScalarsAndPtrs)

314 .legalFor(allowedVectorTypes)

319

321

334

335

336

342 typeInSet(1, allPtrsScalarsAndVectors)));

343

346 typeInSet(1, allFloatScalarsAndVectors)));

347

349 G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,

350 G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,

351 G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})

352 .legalForCartesianProduct(allIntScalars, allPtrs);

353

355 {G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB, G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAX})

356 .legalForCartesianProduct(allFloatScalarsAndF16Vector2AndVector4s,

357 allPtrs);

358

361

363

365

367 {G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO})

368 .alwaysLegal();

369

371 .legalForCartesianProduct(allFloatScalarsAndVectors,

372 allIntScalarsAndVectors);

373

374

376 .legalForCartesianProduct(allFloatScalarsAndVectors);

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387 allFloatScalarsAndVectors, {s32, v2s32, v3s32, v4s32, v8s32, v16s32});

388

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394 G_FPOW,

395 G_FEXP,

396 G_FMODF,

397 G_FEXP2,

398 G_FLOG,

399 G_FLOG2,

400 G_FLOG10,

401 G_FABS,

402 G_FMINNUM,

403 G_FMAXNUM,

404 G_FCEIL,

405 G_FCOS,

406 G_FSIN,

407 G_FTAN,

408 G_FACOS,

409 G_FASIN,

410 G_FATAN,

411 G_FATAN2,

412 G_FCOSH,

413 G_FSINH,

414 G_FTANH,

415 G_FSQRT,

416 G_FFLOOR,

417 G_FRINT,

418 G_FNEARBYINT,

419 G_INTRINSIC_ROUND,

420 G_INTRINSIC_TRUNC,

421 G_FMINIMUM,

422 G_FMAXIMUM,

423 G_INTRINSIC_ROUNDEVEN})

424 .legalFor(allFloatScalarsAndVectors);

425

428 allFloatScalarsAndVectors);

429

431 allFloatScalarsAndVectors, allIntScalarsAndVectors);

432

433 if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {

435 {G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})

436 .legalForCartesianProduct(allIntScalarsAndVectors,

437 allIntScalarsAndVectors);

438

439

441 }

442

444

446 verify(*ST.getInstrInfo());

447}

448

452 Register DstReg = MI.getOperand(0).getReg();

453 Register SrcReg = MI.getOperand(1).getReg();

454 Register IdxReg = MI.getOperand(2).getReg();

455

456 MIRBuilder

458 .addUse(SrcReg)

460 MI.eraseFromParent();

461 return true;

462}

463

468 Register ConvReg = MRI.createGenericVirtualRegister(ConvTy);

474 return ConvReg;

475}

476

481 switch (MI.getOpcode()) {

482 default:

483

484 return true;

485 case TargetOpcode::G_BITCAST:

486 return legalizeBitcast(Helper, MI);

487 case TargetOpcode::G_EXTRACT_VECTOR_ELT:

489 case TargetOpcode::G_INTRINSIC:

490 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:

492 case TargetOpcode::G_IS_FPCLASS:

493 return legalizeIsFPClass(Helper, MI, LocObserver);

494 case TargetOpcode::G_ICMP: {

495 assert(GR->getSPIRVTypeForVReg(MI.getOperand(0).getReg()));

496 auto &Op0 = MI.getOperand(2);

497 auto &Op1 = MI.getOperand(3);

498 Register Reg0 = Op0.getReg();

499 Register Reg1 = Op1.getReg();

502 if ((!ST->canDirectlyComparePointers() ||

504 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) {

507 ST->getPointerSize());

508 SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(

509 LLVMTy, Helper.MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);

512 }

513 return true;

514 }

515 }

516}

517

521

525

527 if (IntrinsicID == Intrinsic::spv_bitcast) {

528 LLVM_DEBUG(dbgs() << "Found a bitcast instruction\n");

529 Register DstReg = MI.getOperand(0).getReg();

530 Register SrcReg = MI.getOperand(2).getReg();

531 LLT DstTy = MRI.getType(DstReg);

532 LLT SrcTy = MRI.getType(SrcReg);

533

534 int32_t MaxVectorSize = ST.isShader() ? 4 : 16;

535

536 bool DstNeedsLegalization = false;

537 bool SrcNeedsLegalization = false;

538

542 DstNeedsLegalization = true;

543 }

544

546 DstNeedsLegalization = true;

547 }

548 }

549

550 if (SrcTy.isVector()) {

551 if (SrcTy.getNumElements() > 4 &&

553 SrcNeedsLegalization = true;

554 }

555

556 if (SrcTy.getNumElements() > MaxVectorSize) {

557 SrcNeedsLegalization = true;

558 }

559 }

560

561

562

563 if (DstNeedsLegalization || SrcNeedsLegalization) {

564 LLVM_DEBUG(dbgs() << "Replacing with a G_BITCAST\n");

566 MI.eraseFromParent();

567 }

568 return true;

569 }

570 return true;

571}

572

573bool SPIRVLegalizerInfo::legalizeBitcast(LegalizerHelper &Helper,

575

576

577

578

580 Register DstReg = MI.getOperand(0).getReg();

581 Register SrcReg = MI.getOperand(1).getReg();

584 MI.eraseFromParent();

585 return true;

586}

587

588

589

590

591bool SPIRVLegalizerInfo::legalizeIsFPClass(

594 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();

596

597 auto &MIRBuilder = Helper.MIRBuilder;

598 auto &MF = MIRBuilder.getMF();

599 MachineRegisterInfo &MRI = MF.getRegInfo();

600

601 Type *LLVMDstTy =

603 if (DstTy.isVector())

604 LLVMDstTy = VectorType::get(LLVMDstTy, DstTy.getElementCount());

605 SPIRVType *SPIRVDstTy = GR->getOrCreateSPIRVType(

606 LLVMDstTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,

607 true);

608

609 unsigned BitSize = SrcTy.getScalarSizeInBits();

611

614 if (SrcTy.isVector()) {

615 IntTy = LLT::vector(SrcTy.getElementCount(), IntTy);

616 LLVMIntTy = VectorType::get(LLVMIntTy, SrcTy.getElementCount());

617 }

618 SPIRVType *SPIRVIntTy = GR->getOrCreateSPIRVType(

619 LLVMIntTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,

620 true);

621

622

623 LLT DstTyCopy = DstTy;

624 const auto assignSPIRVTy = [&](MachineInstrBuilder &&MI) {

625

626

627

628 LLT MITy = MRI.getType(MI.getReg(0));

629 assert((MITy == IntTy || MITy == DstTyCopy) &&

630 "Unexpected LLT type while lowering G_IS_FPCLASS");

631 auto *SPVTy = MITy == IntTy ? SPIRVIntTy : SPIRVDstTy;

632 GR->assignSPIRVTypeToVReg(SPVTy, MI.getReg(0), MF);

633 return MI;

634 };

635

636

637 const auto buildSPIRVConstant = [&](LLT Ty, auto &&C) -> MachineInstrBuilder {

639 return assignSPIRVTy(MIRBuilder.buildConstant(Ty, C));

641 assert((Ty == IntTy || Ty == DstTyCopy) &&

642 "Unexpected LLT type while lowering constant for G_IS_FPCLASS");

643 SPIRVType *VecEltTy = GR->getOrCreateSPIRVType(

644 (Ty == IntTy ? LLVMIntTy : LLVMDstTy)->getScalarType(), MIRBuilder,

645 SPIRV::AccessQualifier::ReadWrite,

646 true);

647 GR->assignSPIRVTypeToVReg(VecEltTy, ScalarC.getReg(0), MF);

649 };

650

651 if (Mask == fcNone) {

652 MIRBuilder.buildCopy(DstReg, buildSPIRVConstant(DstTy, 0));

653 MI.eraseFromParent();

654 return true;

655 }

657 MIRBuilder.buildCopy(DstReg, buildSPIRVConstant(DstTy, 1));

658 MI.eraseFromParent();

659 return true;

660 }

661

662

663

664

665

666 Register ResVReg = MRI.createGenericVirtualRegister(IntTy);

667 MRI.setRegClass(ResVReg, GR->getRegClass(SPIRVIntTy));

668 GR->assignSPIRVTypeToVReg(SPIRVIntTy, ResVReg, Helper.MIRBuilder.getMF());

669 auto AsInt = MIRBuilder.buildInstr(SPIRV::OpBitcast)

671 .addUse(GR->getSPIRVTypeID(SPIRVIntTy))

673 AsInt = assignSPIRVTy(std::move(AsInt));

674

675

679 APInt ExpMask = Inf;

681 APInt QNaNBitMask =

683 APInt InversionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());

684

685 auto SignBitC = buildSPIRVConstant(IntTy, SignBit);

686 auto ValueMaskC = buildSPIRVConstant(IntTy, ValueMask);

687 auto InfC = buildSPIRVConstant(IntTy, Inf);

688 auto ExpMaskC = buildSPIRVConstant(IntTy, ExpMask);

689 auto ZeroC = buildSPIRVConstant(IntTy, 0);

690

691 auto Abs = assignSPIRVTy(MIRBuilder.buildAnd(IntTy, AsInt, ValueMaskC));

692 auto Sign = assignSPIRVTy(

694

695 auto Res = buildSPIRVConstant(DstTy, 0);

696

697 const auto appendToRes = [&](MachineInstrBuilder &&ToAppend) {

698 Res = assignSPIRVTy(

699 MIRBuilder.buildOr(DstTyCopy, Res, assignSPIRVTy(std::move(ToAppend))));

700 };

701

702

704

706 ExpMaskC));

707 Mask &= ~fcFinite;

709

711 ExpMaskC));

712 Mask &= ~fcPosFinite;

714

716 DstTy, Abs, ExpMaskC));

717 appendToRes(MIRBuilder.buildAnd(DstTy, Cmp, Sign));

718 Mask &= ~fcNegFinite;

719 }

720

722

723

724

726 auto ExpBits = assignSPIRVTy(MIRBuilder.buildAnd(IntTy, AsInt, ExpMaskC));

728 ExpBits, ZeroC));

729 Mask &= ~PartialCheck;

730 }

731 }

732

733

737 AsInt, ZeroC));

738 else if (PartialCheck == fcZero)

739 appendToRes(

741 else

743 AsInt, SignBitC));

744 }

745

747

748

750 auto OneC = buildSPIRVConstant(IntTy, 1);

751 auto VMinusOne = MIRBuilder.buildSub(IntTy, V, OneC);

752 auto SubnormalRes = assignSPIRVTy(

754 buildSPIRVConstant(IntTy, AllOneMantissa)));

756 SubnormalRes = MIRBuilder.buildAnd(DstTy, SubnormalRes, Sign);

757 appendToRes(std::move(SubnormalRes));

758 }

759

761 if (PartialCheck == fcPosInf)

763 AsInt, InfC));

764 else if (PartialCheck == fcInf)

765 appendToRes(

767 else {

769 auto NegInfC = buildSPIRVConstant(IntTy, NegInf);

771 AsInt, NegInfC));

772 }

773 }

774

776 auto InfWithQnanBitC =

777 buildSPIRVConstant(IntTy, std::move(Inf) | QNaNBitMask);

778 if (PartialCheck == fcNan) {

779

780 appendToRes(

782 } else if (PartialCheck == fcQNan) {

783

785 InfWithQnanBitC));

786 } else {

787

788

789 auto IsNan = assignSPIRVTy(

791 auto IsNotQnan = assignSPIRVTy(MIRBuilder.buildICmp(

793 appendToRes(MIRBuilder.buildAnd(DstTy, IsNan, IsNotQnan));

794 }

795 }

796

798

799

800 APInt ExpLSB = ExpMask & ~(ExpMask.shl(1));

801 auto ExpMinusOne = assignSPIRVTy(

802 MIRBuilder.buildSub(IntTy, Abs, buildSPIRVConstant(IntTy, ExpLSB)));

803 APInt MaxExpMinusOne = std::move(ExpMask) - ExpLSB;

804 auto NormalRes = assignSPIRVTy(

806 buildSPIRVConstant(IntTy, MaxExpMinusOne)));

808 NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, Sign);

810 auto PosSign = assignSPIRVTy(MIRBuilder.buildXor(

811 DstTy, Sign, buildSPIRVConstant(DstTy, InversionMask)));

812 NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, PosSign);

813 }

814 appendToRes(std::move(NormalRes));

815 }

816

817 MIRBuilder.buildCopy(DstReg, Res);

818 MI.eraseFromParent();

819 return true;

820}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static void scalarize(Instruction *I, SmallVectorImpl< Instruction * > &Worklist)

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

This file declares the MachineIRBuilder class.

Promote Memory to Register

const SmallVectorImpl< MachineOperand > & Cond

static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpvType, LegalizerHelper &Helper, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)

Definition SPIRVLegalizerInfo.cpp:464

LegalityPredicate typeOfExtendedScalars(unsigned TypeIdx, bool IsExtendedInts)

Definition SPIRVLegalizerInfo.cpp:33

static bool legalizeExtractVectorElt(LegalizerHelper &Helper, MachineInstr &MI, SPIRVGlobalRegistry *GR)

Definition SPIRVLegalizerInfo.cpp:449

APInt bitcastToAPInt() const

static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)

Returns the largest finite number in the given semantics.

static APFloat getInf(const fltSemantics &Sem, bool Negative=false)

Factory for Positive and Negative Infinity.

static APInt getAllOnes(unsigned numBits)

Return an APInt of a specified width with all bits set.

static APInt getSignMask(unsigned BitWidth)

Get the SignMask for a specific bit width.

unsigned getActiveBits() const

Compute the number of active bits in the value.

static APInt getSignedMaxValue(unsigned numBits)

Gets maximum signed value of APInt for a specific bit width.

APInt shl(unsigned shiftAmt) const

Left-shift function.

static APInt getOneBitSet(unsigned numBits, unsigned BitNo)

Return an APInt with exactly one bit set in the result.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

@ ICMP_UGE

unsigned greater or equal

@ ICMP_UGT

unsigned greater than

@ ICMP_ULT

unsigned less than

static constexpr ElementCount getFixed(ScalarTy MinVal)

static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)

This static method is the primary way of constructing an IntegerType.

static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)

Get a low-level vector of some number of elements and element width.

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isValid() const

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)

Get a low-level pointer in the given address space.

static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)

Get a low-level fixed-width vector of some number of elements and element width.

constexpr bool isPointerOrPointerVector() const

constexpr bool isFixedVector() const

Returns true if the LLT is a fixed vector.

constexpr LLT getScalarType() const

LLVM_ABI void computeTables()

Compute any ancillary tables needed to quickly decide how an operation should be handled.

LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)

The instruction is legal when type index 0 is any type in the given list.

LegalizeRuleSet & fewerElementsIf(LegalityPredicate Predicate, LegalizeMutation Mutation)

Remove elements to reach the type selected by the mutation if the predicate is true.

LegalizeRuleSet & moreElementsToNextPow2(unsigned TypeIdx)

Add more elements to the vector to reach the next power of two.

LegalizeRuleSet & lower()

The instruction is lowered.

LegalizeRuleSet & lowerIf(LegalityPredicate Predicate)

The instruction is lowered if predicate is true.

LegalizeRuleSet & custom()

Unconditionally custom lower.

LegalizeRuleSet & unsupportedIf(LegalityPredicate Predicate)

LegalizeRuleSet & alwaysLegal()

LegalizeRuleSet & customIf(LegalityPredicate Predicate)

LegalizeRuleSet & scalarize(unsigned TypeIdx)

LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)

The instruction is legal when type indexes 0 and 1 are both in the given list.

LegalizeRuleSet & legalIf(LegalityPredicate Predicate)

The instruction is legal if predicate is true.

MachineIRBuilder & MIRBuilder

Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.

LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)

Get the action definition builder for the given opcode.

const LegacyLegalizerInfo & getLegacyLegalizerInfo() const

Helper class to build MachineInstr.

LLVMContext & getContext() const

MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)

Build and insert Res = G_AND Op0, Op1.

MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_ICMP Pred, Op0, Op1.

MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_SUB Op0, Op1.

MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)

Build and insert a G_INTRINSIC instruction.

MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

MachineFunction & getMF()

Getter for the function we currently build.

MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)

Build and insert Dst = G_BITCAST Src.

MachineRegisterInfo * getMRI()

Getter for MRI.

MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_OR Op0, Op1.

MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)

Build and insert Res = COPY Op.

MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)

Build and insert Res = G_XOR Op0, Op1.

virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)

Build and insert Res = G_CONSTANT Val.

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Wrapper class representing virtual and physical registers.

void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, const MachineFunction &MF)

const TargetRegisterClass * getRegClass(SPIRVType *SpvType) const

SPIRVLegalizerInfo(const SPIRVSubtarget &ST)

Definition SPIRVLegalizerInfo.cpp:40

bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override

Called for instructions with the Custom LegalizationAction.

Definition SPIRVLegalizerInfo.cpp:477

bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override

Definition SPIRVLegalizerInfo.cpp:518

SPIRVGlobalRegistry * getSPIRVGlobalRegistry() const

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

The instances of the Type class are immutable: once they are created, they are never changed.

static LLVM_ABI VectorType * get(Type *ElementType, ElementCount EC)

This static method is the primary way to construct an VectorType.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

@ C

The default llvm calling convention, compatible with C.

LLVM_ABI LegalityPredicate vectorElementCountIsLessThanOrEqualTo(unsigned TypeIdx, unsigned Size)

True iff the specified type index is a vector with a number of elements that's less than or equal to ...

LLVM_ABI LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)

True iff the given type index is one of the specified types.

LLVM_ABI LegalityPredicate vectorElementCountIsGreaterThan(unsigned TypeIdx, unsigned Size)

True iff the specified type index is a vector with a number of elements that's greater than the given...

Predicate any(Predicate P0, Predicate P1)

True iff P0 or P1 are true.

LegalityPredicate typeIsNot(unsigned TypeIdx, LLT Type)

True iff the given type index is not the specified type.

Predicate all(Predicate P0, Predicate P1)

True iff P0 and P1 are true.

LLVM_ABI LegalityPredicate typeIs(unsigned TypeIdx, LLT TypesInit)

True iff the given type index is the specified type.

LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx, unsigned FromTypeIdx)

Keep the same scalar or element type as TypeIdx, but take the number of elements from FromTypeIdx.

LLVM_ABI LegalizeMutation changeElementSizeTo(unsigned TypeIdx, unsigned FromTypeIdx)

Change the scalar size or element size to have the same scalar size as type index FromIndex.

Invariant opcodes: All instruction sets have these as their low opcodes.

This is an optimization pass for GlobalISel generic memory operations.

LLVM_ABI const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)

Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.

std::function< bool(const LegalityQuery &)> LegalityPredicate

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

FPClassTest

Floating-point class tests, supported by 'is_fpclass' intrinsic.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

const MachineInstr SPIRVType

const std::set< unsigned > & getTypeFoldingSupportedOpcodes()

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

The LegalityQuery object bundles together all the information that's needed to decide whether a given...