ScheduleDAGFast.cpp Source File (original) (raw)

26using namespace llvm;

28#define DEBUG_TYPE "pre-RA-sched"

30 STATISTIC(NumUnfolds, "Number of nodes unfolded");

31 STATISTIC(NumDups, "Number of duplicated nodes");

32 STATISTIC(NumPRCopies, "Number of physical copies");

42namespace {

46 struct FastPriorityQueue {

49 bool empty() const { return Queue.empty(); }

51 void push(SUnit *U) {

52 Queue.push_back(U);

53 }

55 SUnit *pop() {

56 if (empty()) return nullptr;

57 return Queue.pop_back_val();

58 }

59 };

65private:

67 FastPriorityQueue AvailableQueue;

72 unsigned NumLiveRegs = 0u;

73 std::vector<SUnit*> LiveRegDefs;

74 std::vector LiveRegCycles;

76public:

77 ScheduleDAGFast(MachineFunction &mf)

78 : ScheduleDAGSDNodes(mf) {}

80 void Schedule() override;

83 void AddPred(SUnit *SU, const SDep &D) { SU->addPred(D); }

86 void RemovePred(SUnit *SU, const SDep &D) { SU->removePred(D); }

88private:

89 void ReleasePred(SUnit *SU, SDep *PredEdge);

90 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);

91 void ScheduleNodeBottomUp(SUnit*, unsigned);

92 SUnit *CopyAndMoveSuccessors(SUnit*);

93 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,

94 const TargetRegisterClass*,

95 const TargetRegisterClass*,

96 SmallVectorImpl<SUnit*>&);

97 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl&);

98 void ListScheduleBottomUp();

100

101 bool forceUnitLatencies() const override { return true; }

102};

103}

104

105

106

107void ScheduleDAGFast::Schedule() {

108 LLVM_DEBUG(dbgs() << "********** List Scheduling **********\n");

109

110 NumLiveRegs = 0;

111 LiveRegDefs.resize(TRI->getNumRegs(), nullptr);

112 LiveRegCycles.resize(TRI->getNumRegs(), 0);

113

114

115 BuildSchedGraph();

116

118

119

120 ListScheduleBottomUp();

121}

122

123

124

125

126

127

128

129void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {

130 SUnit *PredSU = PredEdge->getSUnit();

131

132#ifndef NDEBUG

134 dbgs() << "*** Scheduling failed! ***\n";

135 dumpNode(*PredSU);

136 dbgs() << " has been released too many times!\n";

138 }

139#endif

141

142

143

144 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {

146 AvailableQueue.push(PredSU);

147 }

148}

149

150void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) {

151

152 for (SDep &Pred : SU->Preds) {

153 ReleasePred(SU, &Pred);

155

156

157

158

159 if (!LiveRegDefs[Pred.getReg()]) {

160 ++NumLiveRegs;

162 LiveRegCycles[Pred.getReg()] = CurCycle;

163 }

164 }

165 }

166}

167

168

169

170

171void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {

172 LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");

174

175 assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!");

178

179 ReleasePredecessors(SU, CurCycle);

180

181

182 for (SDep &Succ : SU->Succs) {

185 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");

187 "Physical register dependency violated?");

188 --NumLiveRegs;

189 LiveRegDefs[Succ.getReg()] = nullptr;

190 LiveRegCycles[Succ.getReg()] = 0;

191 }

192 }

193 }

194

196}

197

198

199

200SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {

202 return nullptr;

203

205 if ()

206 return nullptr;

207

208 SUnit *NewSU;

209 bool TryUnfold = false;

210 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {

211 MVT VT = N->getSimpleValueType(i);

212 if (VT == MVT::Glue)

213 return nullptr;

214 else if (VT == MVT::Other)

215 TryUnfold = true;

216 }

217 for (const SDValue &Op : N->op_values()) {

218 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());

219 if (VT == MVT::Glue)

220 return nullptr;

221 }

222

223 if (TryUnfold) {

225 if ( TII ->unfoldMemoryOperand(*DAG, N, NewNodes))

226 return nullptr;

227

229 assert(NewNodes.size() == 2 && "Expected a load folding node!");

230

231 N = NewNodes[1];

232 SDNode *LoadNode = NewNodes[0];

233 unsigned NumVals = N->getNumValues();

235 for (unsigned i = 0; i != NumVals; ++i)

237 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),

239

240 SUnit *NewSU = newSUnit(N);

241 assert(N->getNodeId() == -1 && "Node already inserted!");

242 N->setNodeId(NewSU->NodeNum);

243

244 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());

245 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {

248 break;

249 }

250 }

253

254

255

256

257 bool isNewLoad = true;

258 SUnit *LoadSU;

259 if (LoadNode->getNodeId() != -1) {

260 LoadSU = &SUnits[LoadNode->getNodeId()];

261 isNewLoad = false;

262 } else {

263 LoadSU = newSUnit(LoadNode);

265 }

266

267 SDep ChainPred;

272 for (SDep &Pred : SU->Preds) {

274 ChainPred = Pred;

278 else

280 }

281 for (SDep &Succ : SU->Succs) {

284 else

286 }

287

289 RemovePred(SU, ChainPred);

290 if (isNewLoad)

291 AddPred(LoadSU, ChainPred);

292 }

293 for (const SDep &Pred : LoadPreds) {

294 RemovePred(SU, Pred);

295 if (isNewLoad) {

296 AddPred(LoadSU, Pred);

297 }

298 }

299 for (const SDep &Pred : NodePreds) {

300 RemovePred(SU, Pred);

301 AddPred(NewSU, Pred);

302 }

303 for (SDep D : NodeSuccs) {

304 SUnit *SuccDep = D.getSUnit();

305 D.setSUnit(SU);

306 RemovePred(SuccDep, D);

307 D.setSUnit(NewSU);

308 AddPred(SuccDep, D);

309 }

310 for (SDep D : ChainSuccs) {

311 SUnit *SuccDep = D.getSUnit();

312 D.setSUnit(SU);

313 RemovePred(SuccDep, D);

314 if (isNewLoad) {

315 D.setSUnit(LoadSU);

316 AddPred(SuccDep, D);

317 }

318 }

319 if (isNewLoad) {

321 D.setLatency(LoadSU->Latency);

322 AddPred(NewSU, D);

323 }

324

325 ++NumUnfolds;

326

329 return NewSU;

330 }

331 SU = NewSU;

332 }

333

335 NewSU = Clone(SU);

336

337

338 for (SDep &Pred : SU->Preds)

340 AddPred(NewSU, Pred);

341

342

343

345 for (SDep &Succ : SU->Succs) {

347 continue;

348 SUnit *SuccSU = Succ.getSUnit();

350 SDep D = Succ;

352 AddPred(SuccSU, D);

353 D.setSUnit(SU);

354 DelDeps.push_back(std::make_pair(SuccSU, D));

355 }

356 }

357 for (const auto &[Del, Dep] : DelDeps)

358 RemovePred(Del, Dep);

359

360 ++NumDups;

361 return NewSU;

362}

363

364

365

366void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,

367 const TargetRegisterClass *DestRC,

368 const TargetRegisterClass *SrcRC,

369 SmallVectorImpl<SUnit*> &Copies) {

370 SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(nullptr));

373

374 SUnit *CopyToSU = newSUnit(static_cast<SDNode *>(nullptr));

377

378

379

381 for (SDep &Succ : SU->Succs) {

383 continue;

384 SUnit *SuccSU = Succ.getSUnit();

386 SDep D = Succ;

388 AddPred(SuccSU, D);

389 DelDeps.push_back(std::make_pair(SuccSU, Succ));

390 }

391 }

392 for (const auto &[Del, Dep] : DelDeps)

393 RemovePred(Del, Dep);

395 FromDep.setLatency(SU->Latency);

396 AddPred(CopyFromSU, FromDep);

397 SDep ToDep(CopyFromSU, SDep::Data, 0);

398 ToDep.setLatency(CopyFromSU->Latency);

399 AddPred(CopyToSU, ToDep);

400

401 Copies.push_back(CopyFromSU);

402 Copies.push_back(CopyToSU);

403

404 ++NumPRCopies;

405}

406

407

408

409

412 unsigned NumRes;

414

415 NumRes = 1;

416 } else {

418 assert( MCID .implicit_defs().empty() &&

419 "Physical reg def must be in implicit def list!");

420 NumRes = MCID.getNumDefs();

422 if (Reg == ImpDef)

423 break;

424 ++NumRes;

425 }

426 }

427 return N->getSimpleValueType(NumRes);

428}

429

430

431

433 std::vector<SUnit *> &LiveRegDefs,

438 bool Added = false;

440

441 if (!LiveRegDefs[*AI])

442 continue;

443

444

445 if (LiveRegDefs[*AI] == SU)

446 continue;

447

448

450 continue;

451

452

453 if (RegAdded.insert(*AI).second) {

455 Added = true;

456 }

457 }

458 return Added;

459}

460

461

462

463

464

465bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,

466 SmallVectorImpl &LRegs){

467 if (NumLiveRegs == 0)

468 return false;

469

470 SmallSet<unsigned, 4> RegAdded;

471

472 for (SDep &Pred : SU->Preds) {

475 RegAdded, LRegs, TRI);

476 }

477 }

478

479 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {

480 if (Node->getOpcode() == ISD::INLINEASM ||

481 Node->getOpcode() == ISD::INLINEASM_BR) {

482

483 unsigned NumOps = Node->getNumOperands();

484 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)

485 --NumOps;

486

488 unsigned Flags = Node->getConstantOperandVal(i);

489 const InlineAsm::Flag F(Flags);

490 unsigned NumVals = F.getNumOperandRegisters();

491

492 ++i;

493 if (F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||

494 F.isClobberKind()) {

495

496 for (; NumVals; --NumVals, ++i) {

500 }

501 } else

502 i += NumVals;

503 }

504 continue;

505 }

506

510 SDNode *SrcNode = Node->getOperand(2).getNode();

512 }

513 }

514

515 if ( Node ->isMachineOpcode())

516 continue;

517 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());

520 }

521 return !LRegs.empty();

522}

523

524

525

526

527void ScheduleDAGFast::ListScheduleBottomUp() {

528 unsigned CurCycle = 0;

529

530

531 ReleasePredecessors(&ExitSU, CurCycle);

532

533

534 if (!SUnits.empty()) {

535 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];

536 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");

538 AvailableQueue.push(RootSU);

539 }

540

541

542

544 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;

545 Sequence.reserve(SUnits.size());

546 while (!AvailableQueue.empty()) {

547 bool Delayed = false;

548 LRegsMap.clear();

549 SUnit *CurSU = AvailableQueue.pop();

550 while (CurSU) {

551 SmallVector<unsigned, 4> LRegs;

552 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))

553 break;

554 Delayed = true;

555 LRegsMap.insert(std::make_pair(CurSU, LRegs));

556

557 CurSU->isPending = true;

559 CurSU = AvailableQueue.pop();

560 }

561

562

563

564

565 if (Delayed && !CurSU) {

566 if (!CurSU) {

567

568

569

570 SUnit *TrySU = NotReady[0];

571 SmallVectorImpl &LRegs = LRegsMap[TrySU];

572 assert(LRegs.size() == 1 && "Can't handle this yet!");

573 unsigned Reg = LRegs[0];

574 SUnit *LRDef = LiveRegDefs[Reg];

576 const TargetRegisterClass *RC =

577 TRI->getMinimalPhysRegClass(Reg, VT);

578 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);

579

580

581

582

583

584

585

586

587 SUnit *NewDef = nullptr;

588 if (DestRC != RC) {

589 NewDef = CopyAndMoveSuccessors(LRDef);

590 if (!DestRC && !NewDef)

592 "register dependency!");

593 }

594 if (!NewDef) {

595

597 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);

599 << " to SU #" << Copies.front()->NodeNum << "\n");

601 NewDef = Copies.back();

602 }

603

605 << " to SU #" << TrySU->NodeNum << "\n");

606 LiveRegDefs[Reg] = NewDef;

609 CurSU = NewDef;

610 }

611

612 if (!CurSU) {

613 llvm_unreachable("Unable to resolve live physical register dependencies!");

614 }

615 }

616

617

618 for (SUnit *SU : NotReady) {

620

622 AvailableQueue.push(SU);

623 }

624 NotReady.clear();

625

626 if (CurSU)

627 ScheduleNodeBottomUp(CurSU, CurCycle);

628 ++CurCycle;

629 }

630

631

633

634#ifndef NDEBUG

635 VerifyScheduledSequence(true);

636#endif

637}

638

639

640namespace {

641

642

643

644

645

646class ScheduleDAGLinearize : public ScheduleDAGSDNodes {

647public:

648 ScheduleDAGLinearize(MachineFunction &mf) : ScheduleDAGSDNodes(mf) {}

649

650 void Schedule() override;

651

652 MachineBasicBlock *

654

655private:

656 std::vector<SDNode*> Sequence;

657 DenseMap<SDNode*, SDNode*> GluedMap;

658

659 void ScheduleNode(SDNode *N);

660};

661}

662

663void ScheduleDAGLinearize::ScheduleNode(SDNode *N) {

664 if (N->getNodeId() != 0)

666

667 if (->isMachineOpcode() &&

669

670 return;

671

674 Sequence.push_back(N);

675

676 unsigned NumOps = N->getNumOperands();

677 if (unsigned NumLeft = NumOps) {

678 SDNode *GluedOpN = nullptr;

679 do {

680 const SDValue &Op = N->getOperand(NumLeft-1);

681 SDNode *OpN = Op.getNode();

682

683 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {

684

685 GluedOpN = OpN;

686 assert(OpN->getNodeId() != 0 && "Glue operand not ready?");

688 ScheduleNode(OpN);

689 continue;

690 }

691

692 if (OpN == GluedOpN)

693

694 continue;

695

696 DenseMap<SDNode*, SDNode*>::iterator DI = GluedMap.find(OpN);

697 if (DI != GluedMap.end() && DI->second != N)

698

699 OpN = DI->second;

700

701 unsigned Degree = OpN->getNodeId();

702 assert(Degree > 0 && "Predecessor over-released!");

704 if (Degree == 0)

705 ScheduleNode(OpN);

706 } while (--NumLeft);

707 }

708}

709

710

711

713 while (SDNode *Glued = N->getGluedUser())

714 N = Glued;

715 return N;

716}

717

718void ScheduleDAGLinearize::Schedule() {

719 LLVM_DEBUG(dbgs() << "********** DAG Linearization **********\n");

720

722 unsigned DAGSize = 0;

723 for (SDNode &Node : DAG->allnodes()) {

724 SDNode *N = &Node;

725

726

727 unsigned Degree = N->use_size();

728 N->setNodeId(Degree);

729 unsigned NumVals = N->getNumValues();

730 if (NumVals && N->getValueType(NumVals-1) == MVT::Glue &&

731 N->hasAnyUseOfValue(NumVals-1)) {

733 if (User) {

735 GluedMap.insert(std::make_pair(N, User));

736 }

737 }

738

739 if (N->isMachineOpcode() ||

741 ++DAGSize;

742 }

743

744 for (SDNode *Glue : Glues) {

745 SDNode *GUser = GluedMap[Glue];

746 unsigned Degree = Glue->getNodeId();

747 unsigned UDegree = GUser->getNodeId();

748

749

750

751 SDNode *ImmGUser = Glue->getGluedUser();

752 for (const SDNode *U : Glue->users())

753 if (U == ImmGUser)

754 --Degree;

755 GUser->setNodeId(UDegree + Degree);

756 Glue->setNodeId(1);

757 }

758

759 Sequence.reserve(DAGSize);

760 ScheduleNode(DAG->getRoot().getNode());

761}

762

763MachineBasicBlock*

765 InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);

767

768 LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; });

769

770 unsigned NumNodes = Sequence.size();

771 MachineBasicBlock *BB = Emitter.getBlock();

772 for (unsigned i = 0; i != NumNodes; ++i) {

773 SDNode *N = Sequence[NumNodes-i-1];

775 Emitter.EmitNode(N, false, false, VRBaseMap);

776

777

778 if (N->getHasDebugValue()) {

780 for (auto *DV : DAG->GetDbgValues(N)) {

781 if (!DV->isEmitted())

782 if (auto *DbgMI = Emitter.EmitDbgValue(DV, VRBaseMap))

783 BB->insert(InsertPos, DbgMI);

784 }

785 }

786 }

787

789

790 InsertPos = Emitter.getInsertPos();

791 return Emitter.getBlock();

792}

793

794

795

796

797

800 return new ScheduleDAGFast(*IS->MF);

801}

802

805 return new ScheduleDAGLinearize(*IS->MF);

806}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static msgpack::DocNode getNode(msgpack::DocNode DN, msgpack::Type Type, MCValue Val)

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

dxil DXContainer Global Emitter

const HexagonInstrInfo * TII

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

Promote Memory to Register

static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII)

getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified no...

Definition ScheduleDAGFast.cpp:410

static RegisterScheduler fastDAGScheduler("fast", "Fast suboptimal list scheduling", createFastDAGScheduler)

static bool CheckForLiveRegDef(SUnit *SU, MCRegister Reg, std::vector< SUnit * > &LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs, const TargetRegisterInfo *TRI, const SDNode *Node=nullptr)

CheckForLiveRegDef - Return true and update live register vector if the specified register def of the...

Definition ScheduleDAGFast.cpp:432

static RegisterScheduler linearizeDAGScheduler("linearize", "Linearize DAG, no scheduling", createDAGLinearizer)

static SDNode * findGluedUser(SDNode *N)

findGluedUser - Find the representative use of a glue value by walking the use chain.

Definition ScheduleDAGFast.cpp:712

This file defines the SmallSet class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)

SmallDenseMap< SDValue, Register, 16 > VRBaseMapType

Describe properties that are true of each instruction in the target description file.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const

Returns the value of the specified operand constraint if it is present.

ArrayRef< MCPhysReg > implicit_defs() const

Return a list of registers that are potentially written by any instance of this machine instruction.

bool isCommutable() const

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...

MCRegAliasIterator enumerates all registers aliasing Reg.

Wrapper class representing physical registers. Should be passed by value.

LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

MachineInstrBundleIterator< MachineInstr > iterator

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Represents one node in the SelectionDAG.

int getNodeId() const

Return the unique node id.

void setNodeId(int Id)

Set unique node id.

unsigned getNumValues() const

Return the number of values defined/returned by this operator.

LLVM_ABI bool isOperandOf(const SDNode *N) const

Return true if this node is an operand of N.

SDNode * getGluedNode() const

If this node has a glue operand, return the node to which the glue operand points.

@ Data

Regular data dependence (aka true-dependence).

@ Barrier

An unknown scheduling barrier.

@ Artificial

Arbitrary strong DAG edge (no real dependence).

bool isAssignedRegDep() const

Tests if this is a Data dependence that is associated with a register.

bool isArtificial() const

Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for c...

bool isCtrl() const

Shorthand for getKind() != SDep::Data.

Returns the register associated with this edge.

Scheduling unit. This is a node in the scheduling DAG.

LLVM_ABI void setHeightToAtLeast(unsigned NewHeight)

If NewHeight is greater than this node's height value, set it to be the new height value.

unsigned NodeNum

Entry # of node in the node vector.

const TargetRegisterClass * CopyDstRC

Is a special copy node if != nullptr.

unsigned getHeight() const

Returns the height of this node, which is the length of the maximum path down to any node which has n...

LLVM_ABI void removePred(const SDep &D)

Removes the specified edge as a pred of the current node if it exists.

unsigned short Latency

Node latency.

bool isPending

True once pending.

bool isScheduled

True once scheduled.

bool isAvailable

True once available.

SmallVector< SDep, 4 > Succs

All sunit successors.

const TargetRegisterClass * CopySrcRC

SDNode * getNode() const

Returns the representative SDNode for this SUnit.

bool isTwoAddress

Is a two-address instruction.

bool isCommutable

Is a commutable instruction.

SmallVector< SDep, 4 > Preds

All sunit predecessors.

LLVM_ABI bool addPred(const SDep &D, bool Required=true)

Adds the specified edge as a pred of the current node if not already.

ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.

SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ CopyFromReg

CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...

@ EntryToken

EntryToken - This is the marker used to indicate the start of a region.

@ CopyToReg

CopyToReg - This node has three operands: a chain, a register number to set to this value,...

@ User

could "use" a pointer

Sequence

A sequence of states that a pointer may go through in which an objc_retain and objc_release are actua...

NodeAddr< NodeBase * > Node

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

LLVM_ABI ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)

createFastDAGScheduler - This creates a "fast" scheduler.

Definition ScheduleDAGFast.cpp:798

LLVM_ABI ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)

createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...

Definition ScheduleDAGFast.cpp:803

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

CodeGenOptLevel

Code generation optimization level.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.