SystemZShortenInst.cpp Source File (original) (raw)

21using namespace llvm;

23#define DEBUG_TYPE "systemz-shorten-inst"

25namespace {

27public:

28 static char ID;

29 SystemZShortenInst();

35 }

37private:

38 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);

42 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);

43 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);

44 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);

49};

51char SystemZShortenInst::ID = 0;

52}

55 "SystemZ Instruction Shortening", false, false)

58 return new SystemZShortenInst();

59}

61SystemZShortenInst::SystemZShortenInst()

66 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 &&

67 .getOperand(0).isTied())

68 MI.tieOperands(0, 1);

69}

74bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,

75 unsigned LLIxH) {

79 unsigned thisSubRegIdx =

80 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32

81 : SystemZ::subreg_l32);

82 unsigned otherSubRegIdx =

83 (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32

84 : SystemZ::subreg_l32);

85 unsigned GR64BitReg =

86 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);

87 Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);

88 if (!LiveRegs.available(OtherReg))

89 return false;

91 uint64_t Imm = MI.getOperand(1).getImm();

93 MI.setDesc(TII->get(LLIxL));

95 return true;

96 }

98 MI.setDesc(TII->get(LLIxH));

100 MI.getOperand(1).setImm(Imm >> 16);

101 return true;

102 }

103 return false;

104}

105

106

107bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {

109 MI.setDesc(TII->get(Opcode));

110 return true;

111 }

112 return false;

113}

114

115

116

117bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {

120 MI.setDesc(TII->get(Opcode));

121 return true;

122 }

123 return false;

124}

125

126

127

128

129bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {

131 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&

133 MI.setDesc(TII->get(Opcode));

135 return true;

136 }

137 return false;

138}

139

140

141

142bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {

143 if (LiveRegs.available(SystemZ::CC) && shortenOn001(MI, Opcode)) {

144 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)

146 return true;

147 }

148 return false;

149}

150

151

152

153

154

155bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {

158 MachineOperand Dest(MI.getOperand(0));

159 MachineOperand Src(MI.getOperand(1));

160 MachineOperand Suppress(MI.getOperand(2));

161 MachineOperand Mode(MI.getOperand(3));

162 MI.removeOperand(3);

163 MI.removeOperand(2);

164 MI.removeOperand(1);

165 MI.removeOperand(0);

166 MI.setDesc(TII->get(Opcode));

167 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)

168 .add(Dest)

170 .add(Src)

171 .add(Suppress);

172 return true;

173 }

174 return false;

175}

176

177bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) {

178 MachineOperand &DstMO = MI.getOperand(0);

179 MachineOperand &LHSMO = MI.getOperand(1);

180 MachineOperand &RHSMO = MI.getOperand(2);

181 MachineOperand &AccMO = MI.getOperand(3);

187 MachineOperand Lhs(LHSMO);

188 MachineOperand Rhs(RHSMO);

189 MachineOperand Src(AccMO);

190 MI.removeOperand(3);

191 MI.removeOperand(2);

192 MI.removeOperand(1);

193 MI.setDesc(TII->get(Opcode));

194 MachineInstrBuilder(*MI.getParent()->getParent(), &MI)

195 .add(Src)

196 .add(Lhs)

197 .add(Rhs);

198 return true;

199 }

200 return false;

201}

202

203

204bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {

206

207

208 LiveRegs.clear();

210

211

213 switch (MI.getOpcode()) {

214 case SystemZ::IILF:

215 Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);

216 break;

217

218 case SystemZ::IIHF:

219 Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);

220 break;

221

222 case SystemZ::WFADB:

223 Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);

224 break;

225

226 case SystemZ::WFASB:

227 Changed |= shortenOn001AddCC(MI, SystemZ::AEBR);

228 break;

229

230 case SystemZ::WFDDB:

231 Changed |= shortenOn001(MI, SystemZ::DDBR);

232 break;

233

234 case SystemZ::WFDSB:

235 Changed |= shortenOn001(MI, SystemZ::DEBR);

236 break;

237

238 case SystemZ::WFIDB:

239 Changed |= shortenFPConv(MI, SystemZ::FIDBRA);

240 break;

241

242 case SystemZ::WFISB:

243 Changed |= shortenFPConv(MI, SystemZ::FIEBRA);

244 break;

245

246 case SystemZ::WLDEB:

247 Changed |= shortenOn01(MI, SystemZ::LDEBR);

248 break;

249

250 case SystemZ::WLEDB:

251 Changed |= shortenFPConv(MI, SystemZ::LEDBRA);

252 break;

253

254 case SystemZ::WFMDB:

255 Changed |= shortenOn001(MI, SystemZ::MDBR);

256 break;

257

258 case SystemZ::WFMSB:

259 Changed |= shortenOn001(MI, SystemZ::MEEBR);

260 break;

261

262 case SystemZ::WFMADB:

263 Changed |= shortenFusedFPOp(MI, SystemZ::MADBR);

264 break;

265

266 case SystemZ::WFMASB:

267 Changed |= shortenFusedFPOp(MI, SystemZ::MAEBR);

268 break;

269

270 case SystemZ::WFMSDB:

271 Changed |= shortenFusedFPOp(MI, SystemZ::MSDBR);

272 break;

273

274 case SystemZ::WFMSSB:

275 Changed |= shortenFusedFPOp(MI, SystemZ::MSEBR);

276 break;

277

278 case SystemZ::WFLCDB:

279 Changed |= shortenOn01(MI, SystemZ::LCDFR);

280 break;

281

282 case SystemZ::WFLCSB:

283 Changed |= shortenOn01(MI, SystemZ::LCDFR_32);

284 break;

285

286 case SystemZ::WFLNDB:

287 Changed |= shortenOn01(MI, SystemZ::LNDFR);

288 break;

289

290 case SystemZ::WFLNSB:

291 Changed |= shortenOn01(MI, SystemZ::LNDFR_32);

292 break;

293

294 case SystemZ::WFLPDB:

295 Changed |= shortenOn01(MI, SystemZ::LPDFR);

296 break;

297

298 case SystemZ::WFLPSB:

299 Changed |= shortenOn01(MI, SystemZ::LPDFR_32);

300 break;

301

302 case SystemZ::WFSQDB:

303 Changed |= shortenOn01(MI, SystemZ::SQDBR);

304 break;

305

306 case SystemZ::WFSQSB:

307 Changed |= shortenOn01(MI, SystemZ::SQEBR);

308 break;

309

310 case SystemZ::WFSDB:

311 Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);

312 break;

313

314 case SystemZ::WFSSB:

315 Changed |= shortenOn001AddCC(MI, SystemZ::SEBR);

316 break;

317

318 case SystemZ::WFCDB:

319 Changed |= shortenOn01(MI, SystemZ::CDBR);

320 break;

321

322 case SystemZ::WFCSB:

323 Changed |= shortenOn01(MI, SystemZ::CEBR);

324 break;

325

326 case SystemZ::WFKDB:

327 Changed |= shortenOn01(MI, SystemZ::KDBR);

328 break;

329

330 case SystemZ::WFKSB:

331 Changed |= shortenOn01(MI, SystemZ::KEBR);

332 break;

333

334 case SystemZ::VL32:

335

336 Changed |= shortenOn0(MI, SystemZ::LDE32);

337 break;

338

339 case SystemZ::VST32:

340 Changed |= shortenOn0(MI, SystemZ::STE);

341 break;

342

343 case SystemZ::VL64:

344 Changed |= shortenOn0(MI, SystemZ::LD);

345 break;

346

347 case SystemZ::VST64:

348 Changed |= shortenOn0(MI, SystemZ::STD);

349 break;

350

351 default: {

353 if (TwoOperandOpcode == -1)

354 break;

355

356 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&

357 (.isCommutable() ||

358 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||

359 TII ->commuteInstruction(MI, false, 1, 2)))

360 break;

361

362 MI.setDesc(TII->get(TwoOperandOpcode));

363 MI.tieOperands(0, 1);

364 if (TwoOperandOpcode == SystemZ::SLL ||

365 TwoOperandOpcode == SystemZ::SLA ||

366 TwoOperandOpcode == SystemZ::SRL ||

367 TwoOperandOpcode == SystemZ::SRA) {

368

369 MachineOperand &ImmMO = MI.getOperand(3);

371 }

373 break;

374 }

375 }

376

378 }

379

381}

382

383bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {

384 if (skipFunction(F.getFunction()))

385 return false;

386

387 const SystemZSubtarget &ST = F.getSubtarget();

388 TII = ST.getInstrInfo();

389 TRI = ST.getRegisterInfo();

391

393 for (auto &MBB : F)

395

397}

const HexagonInstrInfo * TII

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))

static void tieOpsIfNeeded(MachineInstr &MI)

Definition SystemZShortenInst.cpp:65

FunctionPass class - This class is used to implement most global optimizations.

A set of register units used to track register liveness.

bool available(MCRegister Reg) const

Returns true if no part of physical register Reg is live.

void init(const TargetRegisterInfo &TRI)

Initialize and clear the set.

LLVM_ABI void stepBackward(const MachineInstr &MI)

Updates liveness when stepping backwards over the instruction MI.

LLVM_ABI void addLiveOuts(const MachineBasicBlock &MBB)

Adds registers living out of block MBB.

void clear()

Clears the set.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

Properties which a MachineFunction may have at a given point in time.

Representation of each machine instruction.

void setImm(int64_t immVal)

getReg - Returns the register number.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

unsigned getFirstReg(unsigned Reg)

unsigned getRegAsGR64(unsigned Reg)

static bool isImmLL(uint64_t Val)

static bool isImmLH(uint64_t Val)

int getTwoOperandOpcode(uint16_t Opcode)

This is an optimization pass for GlobalISel generic memory operations.

auto reverse(ContainerTy &&C)

FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)