TargetLoweringBase.cpp Source File (original) (raw)

58#include

59#include

60#include

61#include

62#include

63#include

64#include

66using namespace llvm;

69 "jump-is-expensive", cl::init(false),

70 cl::desc("Do not create extra branches to split comparison logic."),

75 cl::desc("Set minimum number of entries to use a jump table."));

79 cl::desc("Set maximum size of jump tables."));

84 cl::desc("Minimum density for building a jump table in "

85 "a normal function"));

90 cl::desc("Minimum density for building a jump table in "

91 "an optsize function"));

95 cl::desc("Set minimum of largest number of comparisons "

96 "to use bit test for switch."));

100

101

103 cl::desc("Don't mutate strict-float node to a legalize node"),

105

107 if (VT == MVT::i16)

108 return RTLIB::SHL_I16;

109 if (VT == MVT::i32)

110 return RTLIB::SHL_I32;

111 if (VT == MVT::i64)

112 return RTLIB::SHL_I64;

113 if (VT == MVT::i128)

114 return RTLIB::SHL_I128;

115

116 return RTLIB::UNKNOWN_LIBCALL;

117}

118

120 if (VT == MVT::i16)

121 return RTLIB::SRL_I16;

122 if (VT == MVT::i32)

123 return RTLIB::SRL_I32;

124 if (VT == MVT::i64)

125 return RTLIB::SRL_I64;

126 if (VT == MVT::i128)

127 return RTLIB::SRL_I128;

128

129 return RTLIB::UNKNOWN_LIBCALL;

130}

131

133 if (VT == MVT::i16)

134 return RTLIB::SRA_I16;

135 if (VT == MVT::i32)

136 return RTLIB::SRA_I32;

137 if (VT == MVT::i64)

138 return RTLIB::SRA_I64;

139 if (VT == MVT::i128)

140 return RTLIB::SRA_I128;

141

142 return RTLIB::UNKNOWN_LIBCALL;

143}

144

146 if (VT == MVT::i16)

147 return RTLIB::MUL_I16;

148 if (VT == MVT::i32)

149 return RTLIB::MUL_I32;

150 if (VT == MVT::i64)

151 return RTLIB::MUL_I64;

152 if (VT == MVT::i128)

153 return RTLIB::MUL_I128;

154 return RTLIB::UNKNOWN_LIBCALL;

155}

156

158 if (VT == MVT::i32)

159 return RTLIB::MULO_I32;

160 if (VT == MVT::i64)

161 return RTLIB::MULO_I64;

162 if (VT == MVT::i128)

163 return RTLIB::MULO_I128;

164 return RTLIB::UNKNOWN_LIBCALL;

165}

166

168 if (VT == MVT::i16)

169 return RTLIB::SDIV_I16;

170 if (VT == MVT::i32)

171 return RTLIB::SDIV_I32;

172 if (VT == MVT::i64)

173 return RTLIB::SDIV_I64;

174 if (VT == MVT::i128)

175 return RTLIB::SDIV_I128;

176 return RTLIB::UNKNOWN_LIBCALL;

177}

178

180 if (VT == MVT::i16)

181 return RTLIB::UDIV_I16;

182 if (VT == MVT::i32)

183 return RTLIB::UDIV_I32;

184 if (VT == MVT::i64)

185 return RTLIB::UDIV_I64;

186 if (VT == MVT::i128)

187 return RTLIB::UDIV_I128;

188 return RTLIB::UNKNOWN_LIBCALL;

189}

190

192 if (VT == MVT::i16)

193 return RTLIB::SREM_I16;

194 if (VT == MVT::i32)

195 return RTLIB::SREM_I32;

196 if (VT == MVT::i64)

197 return RTLIB::SREM_I64;

198 if (VT == MVT::i128)

199 return RTLIB::SREM_I128;

200 return RTLIB::UNKNOWN_LIBCALL;

201}

202

204 if (VT == MVT::i16)

205 return RTLIB::UREM_I16;

206 if (VT == MVT::i32)

207 return RTLIB::UREM_I32;

208 if (VT == MVT::i64)

209 return RTLIB::UREM_I64;

210 if (VT == MVT::i128)

211 return RTLIB::UREM_I128;

212 return RTLIB::UNKNOWN_LIBCALL;

213}

214

216 if (VT == MVT::i32)

217 return RTLIB::CTPOP_I32;

218 if (VT == MVT::i64)

219 return RTLIB::CTPOP_I64;

220 if (VT == MVT::i128)

221 return RTLIB::CTPOP_I128;

222 return RTLIB::UNKNOWN_LIBCALL;

223}

224

225

226

228 RTLIB::Libcall Call_F32,

229 RTLIB::Libcall Call_F64,

230 RTLIB::Libcall Call_F80,

231 RTLIB::Libcall Call_F128,

232 RTLIB::Libcall Call_PPCF128) {

233 return

234 VT == MVT::f32 ? Call_F32 :

235 VT == MVT::f64 ? Call_F64 :

236 VT == MVT::f80 ? Call_F80 :

237 VT == MVT::f128 ? Call_F128 :

238 VT == MVT::ppcf128 ? Call_PPCF128 :

239 RTLIB::UNKNOWN_LIBCALL;

240}

241

242

243

245 if (OpVT == MVT::f16) {

246 if (RetVT == MVT::f32)

247 return FPEXT_F16_F32;

248 if (RetVT == MVT::f64)

249 return FPEXT_F16_F64;

250 if (RetVT == MVT::f80)

251 return FPEXT_F16_F80;

252 if (RetVT == MVT::f128)

253 return FPEXT_F16_F128;

254 } else if (OpVT == MVT::f32) {

255 if (RetVT == MVT::f64)

256 return FPEXT_F32_F64;

257 if (RetVT == MVT::f128)

258 return FPEXT_F32_F128;

259 if (RetVT == MVT::ppcf128)

260 return FPEXT_F32_PPCF128;

261 } else if (OpVT == MVT::f64) {

262 if (RetVT == MVT::f128)

263 return FPEXT_F64_F128;

264 else if (RetVT == MVT::ppcf128)

265 return FPEXT_F64_PPCF128;

266 } else if (OpVT == MVT::f80) {

267 if (RetVT == MVT::f128)

268 return FPEXT_F80_F128;

269 } else if (OpVT == MVT::bf16) {

270 if (RetVT == MVT::f32)

271 return FPEXT_BF16_F32;

272 }

273

274 return UNKNOWN_LIBCALL;

275}

276

277

278

280 if (RetVT == MVT::f16) {

281 if (OpVT == MVT::f32)

282 return FPROUND_F32_F16;

283 if (OpVT == MVT::f64)

284 return FPROUND_F64_F16;

285 if (OpVT == MVT::f80)

286 return FPROUND_F80_F16;

287 if (OpVT == MVT::f128)

288 return FPROUND_F128_F16;

289 if (OpVT == MVT::ppcf128)

290 return FPROUND_PPCF128_F16;

291 } else if (RetVT == MVT::bf16) {

292 if (OpVT == MVT::f32)

293 return FPROUND_F32_BF16;

294 if (OpVT == MVT::f64)

295 return FPROUND_F64_BF16;

296 if (OpVT == MVT::f80)

297 return FPROUND_F80_BF16;

298 if (OpVT == MVT::f128)

299 return FPROUND_F128_BF16;

300 } else if (RetVT == MVT::f32) {

301 if (OpVT == MVT::f64)

302 return FPROUND_F64_F32;

303 if (OpVT == MVT::f80)

304 return FPROUND_F80_F32;

305 if (OpVT == MVT::f128)

306 return FPROUND_F128_F32;

307 if (OpVT == MVT::ppcf128)

308 return FPROUND_PPCF128_F32;

309 } else if (RetVT == MVT::f64) {

310 if (OpVT == MVT::f80)

311 return FPROUND_F80_F64;

312 if (OpVT == MVT::f128)

313 return FPROUND_F128_F64;

314 if (OpVT == MVT::ppcf128)

315 return FPROUND_PPCF128_F64;

316 } else if (RetVT == MVT::f80) {

317 if (OpVT == MVT::f128)

318 return FPROUND_F128_F80;

319 }

320

321 return UNKNOWN_LIBCALL;

322}

323

324

325

327 if (OpVT == MVT::f16) {

328 if (RetVT == MVT::i32)

329 return FPTOSINT_F16_I32;

330 if (RetVT == MVT::i64)

331 return FPTOSINT_F16_I64;

332 if (RetVT == MVT::i128)

333 return FPTOSINT_F16_I128;

334 } else if (OpVT == MVT::f32) {

335 if (RetVT == MVT::i32)

336 return FPTOSINT_F32_I32;

337 if (RetVT == MVT::i64)

338 return FPTOSINT_F32_I64;

339 if (RetVT == MVT::i128)

340 return FPTOSINT_F32_I128;

341 } else if (OpVT == MVT::f64) {

342 if (RetVT == MVT::i32)

343 return FPTOSINT_F64_I32;

344 if (RetVT == MVT::i64)

345 return FPTOSINT_F64_I64;

346 if (RetVT == MVT::i128)

347 return FPTOSINT_F64_I128;

348 } else if (OpVT == MVT::f80) {

349 if (RetVT == MVT::i32)

350 return FPTOSINT_F80_I32;

351 if (RetVT == MVT::i64)

352 return FPTOSINT_F80_I64;

353 if (RetVT == MVT::i128)

354 return FPTOSINT_F80_I128;

355 } else if (OpVT == MVT::f128) {

356 if (RetVT == MVT::i32)

357 return FPTOSINT_F128_I32;

358 if (RetVT == MVT::i64)

359 return FPTOSINT_F128_I64;

360 if (RetVT == MVT::i128)

361 return FPTOSINT_F128_I128;

362 } else if (OpVT == MVT::ppcf128) {

363 if (RetVT == MVT::i32)

364 return FPTOSINT_PPCF128_I32;

365 if (RetVT == MVT::i64)

366 return FPTOSINT_PPCF128_I64;

367 if (RetVT == MVT::i128)

368 return FPTOSINT_PPCF128_I128;

369 }

370 return UNKNOWN_LIBCALL;

371}

372

373

374

376 if (OpVT == MVT::f16) {

377 if (RetVT == MVT::i32)

378 return FPTOUINT_F16_I32;

379 if (RetVT == MVT::i64)

380 return FPTOUINT_F16_I64;

381 if (RetVT == MVT::i128)

382 return FPTOUINT_F16_I128;

383 } else if (OpVT == MVT::f32) {

384 if (RetVT == MVT::i32)

385 return FPTOUINT_F32_I32;

386 if (RetVT == MVT::i64)

387 return FPTOUINT_F32_I64;

388 if (RetVT == MVT::i128)

389 return FPTOUINT_F32_I128;

390 } else if (OpVT == MVT::f64) {

391 if (RetVT == MVT::i32)

392 return FPTOUINT_F64_I32;

393 if (RetVT == MVT::i64)

394 return FPTOUINT_F64_I64;

395 if (RetVT == MVT::i128)

396 return FPTOUINT_F64_I128;

397 } else if (OpVT == MVT::f80) {

398 if (RetVT == MVT::i32)

399 return FPTOUINT_F80_I32;

400 if (RetVT == MVT::i64)

401 return FPTOUINT_F80_I64;

402 if (RetVT == MVT::i128)

403 return FPTOUINT_F80_I128;

404 } else if (OpVT == MVT::f128) {

405 if (RetVT == MVT::i32)

406 return FPTOUINT_F128_I32;

407 if (RetVT == MVT::i64)

408 return FPTOUINT_F128_I64;

409 if (RetVT == MVT::i128)

410 return FPTOUINT_F128_I128;

411 } else if (OpVT == MVT::ppcf128) {

412 if (RetVT == MVT::i32)

413 return FPTOUINT_PPCF128_I32;

414 if (RetVT == MVT::i64)

415 return FPTOUINT_PPCF128_I64;

416 if (RetVT == MVT::i128)

417 return FPTOUINT_PPCF128_I128;

418 }

419 return UNKNOWN_LIBCALL;

420}

421

422

423

425 if (OpVT == MVT::i32) {

426 if (RetVT == MVT::f16)

427 return SINTTOFP_I32_F16;

428 if (RetVT == MVT::f32)

429 return SINTTOFP_I32_F32;

430 if (RetVT == MVT::f64)

431 return SINTTOFP_I32_F64;

432 if (RetVT == MVT::f80)

433 return SINTTOFP_I32_F80;

434 if (RetVT == MVT::f128)

435 return SINTTOFP_I32_F128;

436 if (RetVT == MVT::ppcf128)

437 return SINTTOFP_I32_PPCF128;

438 } else if (OpVT == MVT::i64) {

439 if (RetVT == MVT::bf16)

440 return SINTTOFP_I64_BF16;

441 if (RetVT == MVT::f16)

442 return SINTTOFP_I64_F16;

443 if (RetVT == MVT::f32)

444 return SINTTOFP_I64_F32;

445 if (RetVT == MVT::f64)

446 return SINTTOFP_I64_F64;

447 if (RetVT == MVT::f80)

448 return SINTTOFP_I64_F80;

449 if (RetVT == MVT::f128)

450 return SINTTOFP_I64_F128;

451 if (RetVT == MVT::ppcf128)

452 return SINTTOFP_I64_PPCF128;

453 } else if (OpVT == MVT::i128) {

454 if (RetVT == MVT::f16)

455 return SINTTOFP_I128_F16;

456 if (RetVT == MVT::f32)

457 return SINTTOFP_I128_F32;

458 if (RetVT == MVT::f64)

459 return SINTTOFP_I128_F64;

460 if (RetVT == MVT::f80)

461 return SINTTOFP_I128_F80;

462 if (RetVT == MVT::f128)

463 return SINTTOFP_I128_F128;

464 if (RetVT == MVT::ppcf128)

465 return SINTTOFP_I128_PPCF128;

466 }

467 return UNKNOWN_LIBCALL;

468}

469

470

471

473 if (OpVT == MVT::i32) {

474 if (RetVT == MVT::f16)

475 return UINTTOFP_I32_F16;

476 if (RetVT == MVT::f32)

477 return UINTTOFP_I32_F32;

478 if (RetVT == MVT::f64)

479 return UINTTOFP_I32_F64;

480 if (RetVT == MVT::f80)

481 return UINTTOFP_I32_F80;

482 if (RetVT == MVT::f128)

483 return UINTTOFP_I32_F128;

484 if (RetVT == MVT::ppcf128)

485 return UINTTOFP_I32_PPCF128;

486 } else if (OpVT == MVT::i64) {

487 if (RetVT == MVT::bf16)

488 return UINTTOFP_I64_BF16;

489 if (RetVT == MVT::f16)

490 return UINTTOFP_I64_F16;

491 if (RetVT == MVT::f32)

492 return UINTTOFP_I64_F32;

493 if (RetVT == MVT::f64)

494 return UINTTOFP_I64_F64;

495 if (RetVT == MVT::f80)

496 return UINTTOFP_I64_F80;

497 if (RetVT == MVT::f128)

498 return UINTTOFP_I64_F128;

499 if (RetVT == MVT::ppcf128)

500 return UINTTOFP_I64_PPCF128;

501 } else if (OpVT == MVT::i128) {

502 if (RetVT == MVT::f16)

503 return UINTTOFP_I128_F16;

504 if (RetVT == MVT::f32)

505 return UINTTOFP_I128_F32;

506 if (RetVT == MVT::f64)

507 return UINTTOFP_I128_F64;

508 if (RetVT == MVT::f80)

509 return UINTTOFP_I128_F80;

510 if (RetVT == MVT::f128)

511 return UINTTOFP_I128_F128;

512 if (RetVT == MVT::ppcf128)

513 return UINTTOFP_I128_PPCF128;

514 }

515 return UNKNOWN_LIBCALL;

516}

517

519 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,

520 POWI_PPCF128);

521}

522

524 return getFPLibCall(RetVT, POW_F32, POW_F64, POW_F80, POW_F128, POW_PPCF128);

525}

526

528 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,

529 LDEXP_PPCF128);

530}

531

533 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,

534 FREXP_PPCF128);

535}

536

538 return getFPLibCall(RetVT, SIN_F32, SIN_F64, SIN_F80, SIN_F128, SIN_PPCF128);

539}

540

542 return getFPLibCall(RetVT, COS_F32, COS_F64, COS_F80, COS_F128, COS_PPCF128);

543}

544

546

549 return RTLIB::UNKNOWN_LIBCALL;

551 case MVT::v4f32:

552 return RTLIB::SINCOS_V4F32;

553 case MVT::v2f64:

554 return RTLIB::SINCOS_V2F64;

555 case MVT::nxv4f32:

556 return RTLIB::SINCOS_NXV4F32;

557 case MVT::nxv2f64:

558 return RTLIB::SINCOS_NXV2F64;

559 default:

560 return RTLIB::UNKNOWN_LIBCALL;

561 }

562 }

563

564 return getFPLibCall(RetVT, SINCOS_F32, SINCOS_F64, SINCOS_F80, SINCOS_F128,

565 SINCOS_PPCF128);

566}

567

569

572 return RTLIB::UNKNOWN_LIBCALL;

574 case MVT::v4f32:

575 return RTLIB::SINCOSPI_V4F32;

576 case MVT::v2f64:

577 return RTLIB::SINCOSPI_V2F64;

578 case MVT::nxv4f32:

579 return RTLIB::SINCOSPI_NXV4F32;

580 case MVT::nxv2f64:

581 return RTLIB::SINCOSPI_NXV2F64;

582 default:

583 return RTLIB::UNKNOWN_LIBCALL;

584 }

585 }

586

587 return getFPLibCall(RetVT, SINCOSPI_F32, SINCOSPI_F64, SINCOSPI_F80,

588 SINCOSPI_F128, SINCOSPI_PPCF128);

589}

590

592 return getFPLibCall(RetVT, SINCOS_STRET_F32, SINCOS_STRET_F64,

593 UNKNOWN_LIBCALL, UNKNOWN_LIBCALL, UNKNOWN_LIBCALL);

594}

595

597

600 return RTLIB::UNKNOWN_LIBCALL;

602 case MVT::v4f32:

603 return RTLIB::REM_V4F32;

604 case MVT::v2f64:

605 return RTLIB::REM_V2F64;

606 case MVT::nxv4f32:

607 return RTLIB::REM_NXV4F32;

608 case MVT::nxv2f64:

609 return RTLIB::REM_NXV2F64;

610 default:

611 return RTLIB::UNKNOWN_LIBCALL;

612 }

613 }

614

615 return getFPLibCall(VT, REM_F32, REM_F64, REM_F80, REM_F128, REM_PPCF128);

616}

617

619

622 return RTLIB::UNKNOWN_LIBCALL;

624 case MVT::v4f32:

625 return RTLIB::MODF_V4F32;

626 case MVT::v2f64:

627 return RTLIB::MODF_V2F64;

628 case MVT::nxv4f32:

629 return RTLIB::MODF_NXV4F32;

630 case MVT::nxv2f64:

631 return RTLIB::MODF_NXV2F64;

632 default:

633 return RTLIB::UNKNOWN_LIBCALL;

634 }

635 }

636

637 return getFPLibCall(RetVT, MODF_F32, MODF_F64, MODF_F80, MODF_F128,

638 MODF_PPCF128);

639}

640

642 if (VT == MVT::f32)

643 return RTLIB::LROUND_F32;

644 if (VT == MVT::f64)

645 return RTLIB::LROUND_F64;

646 if (VT == MVT::f80)

647 return RTLIB::LROUND_F80;

648 if (VT == MVT::f128)

649 return RTLIB::LROUND_F128;

650 if (VT == MVT::ppcf128)

651 return RTLIB::LROUND_PPCF128;

652

653 return RTLIB::UNKNOWN_LIBCALL;

654}

655

657 if (VT == MVT::f32)

658 return RTLIB::LLROUND_F32;

659 if (VT == MVT::f64)

660 return RTLIB::LLROUND_F64;

661 if (VT == MVT::f80)

662 return RTLIB::LLROUND_F80;

663 if (VT == MVT::f128)

664 return RTLIB::LLROUND_F128;

665 if (VT == MVT::ppcf128)

666 return RTLIB::LLROUND_PPCF128;

667

668 return RTLIB::UNKNOWN_LIBCALL;

669}

670

672 if (VT == MVT::f32)

673 return RTLIB::LRINT_F32;

674 if (VT == MVT::f64)

675 return RTLIB::LRINT_F64;

676 if (VT == MVT::f80)

677 return RTLIB::LRINT_F80;

678 if (VT == MVT::f128)

679 return RTLIB::LRINT_F128;

680 if (VT == MVT::ppcf128)

681 return RTLIB::LRINT_PPCF128;

682 return RTLIB::UNKNOWN_LIBCALL;

683}

684

686 if (VT == MVT::f32)

687 return RTLIB::LLRINT_F32;

688 if (VT == MVT::f64)

689 return RTLIB::LLRINT_F64;

690 if (VT == MVT::f80)

691 return RTLIB::LLRINT_F80;

692 if (VT == MVT::f128)

693 return RTLIB::LLRINT_F128;

694 if (VT == MVT::ppcf128)

695 return RTLIB::LLRINT_PPCF128;

696 return RTLIB::UNKNOWN_LIBCALL;

697}

698

702 unsigned ModeN, ModelN;

703 switch (MemSize) {

704 case 1:

705 ModeN = 0;

706 break;

707 case 2:

708 ModeN = 1;

709 break;

710 case 4:

711 ModeN = 2;

712 break;

713 case 8:

714 ModeN = 3;

715 break;

716 case 16:

717 ModeN = 4;

718 break;

719 default:

720 return RTLIB::UNKNOWN_LIBCALL;

721 }

722

723 switch (Order) {

725 ModelN = 0;

726 break;

728 ModelN = 1;

729 break;

731 ModelN = 2;

732 break;

735 ModelN = 3;

736 break;

737 default:

738 return UNKNOWN_LIBCALL;

739 }

740

741 return LC[ModeN][ModelN];

742}

743

745 MVT VT) {

747 return UNKNOWN_LIBCALL;

749

750#define LCALLS(A, B) \

751 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }

752#define LCALL5(A) \

753 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)

754 switch (Opc) {

755 case ISD::ATOMIC_CMP_SWAP: {

756 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};

758 }

759 case ISD::ATOMIC_SWAP: {

760 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};

762 }

763 case ISD::ATOMIC_LOAD_ADD: {

764 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};

766 }

767 case ISD::ATOMIC_LOAD_OR: {

768 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};

770 }

771 case ISD::ATOMIC_LOAD_CLR: {

772 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};

774 }

775 case ISD::ATOMIC_LOAD_XOR: {

776 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};

778 }

779 default:

780 return UNKNOWN_LIBCALL;

781 }

782#undef LCALLS

783#undef LCALL5

784}

785

787#define OP_TO_LIBCALL(Name, Enum) \

788 case Name: \

789 switch (VT.SimpleTy) { \

790 default: \

791 return UNKNOWN_LIBCALL; \

792 case MVT::i8: \

793 return Enum##_1; \

794 case MVT::i16: \

795 return Enum##_2; \

796 case MVT::i32: \

797 return Enum##_4; \

798 case MVT::i64: \

799 return Enum##_8; \

800 case MVT::i128: \

801 return Enum##_16; \

802 }

803

804 switch (Opc) {

805 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)

806 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)

807 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)

808 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)

809 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)

810 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)

811 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)

812 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)

813 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)

814 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)

815 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)

816 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)

817 }

818

819#undef OP_TO_LIBCALL

820

821 return UNKNOWN_LIBCALL;

822}

823

825 switch (ElementSize) {

826 case 1:

827 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;

828 case 2:

829 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;

830 case 4:

831 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;

832 case 8:

833 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;

834 case 16:

835 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;

836 default:

837 return UNKNOWN_LIBCALL;

838 }

839}

840

842 switch (ElementSize) {

843 case 1:

844 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;

845 case 2:

846 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;

847 case 4:

848 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;

849 case 8:

850 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;

851 case 16:

852 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;

853 default:

854 return UNKNOWN_LIBCALL;

855 }

856}

857

859 switch (ElementSize) {

860 case 1:

861 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;

862 case 2:

863 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;

864 case 4:

865 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;

866 case 8:

867 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;

868 case 16:

869 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;

870 default:

871 return UNKNOWN_LIBCALL;

872 }

873}

874

876 RTLIB::LibcallImpl Impl) const {

877 switch (Impl) {

878 case RTLIB::impl___aeabi_dcmpeq__une:

879 case RTLIB::impl___aeabi_fcmpeq__une:

880

882 case RTLIB::impl___aeabi_dcmpeq__oeq:

883 case RTLIB::impl___aeabi_fcmpeq__oeq:

884

886 case RTLIB::impl___aeabi_dcmplt:

887 case RTLIB::impl___aeabi_dcmple:

888 case RTLIB::impl___aeabi_dcmpge:

889 case RTLIB::impl___aeabi_dcmpgt:

890 case RTLIB::impl___aeabi_dcmpun:

891 case RTLIB::impl___aeabi_fcmplt:

892 case RTLIB::impl___aeabi_fcmple:

893 case RTLIB::impl___aeabi_fcmpge:

894 case RTLIB::impl___aeabi_fcmpgt:

895

896

898 default:

899 break;

900 }

901

902

903

904

905

906

907

909 switch (LC) {

910 case RTLIB::OEQ_F32:

911 case RTLIB::OEQ_F64:

912 case RTLIB::OEQ_F128:

913 case RTLIB::OEQ_PPCF128:

915 case RTLIB::UNE_F32:

916 case RTLIB::UNE_F64:

917 case RTLIB::UNE_F128:

918 case RTLIB::UNE_PPCF128:

920 case RTLIB::OGE_F32:

921 case RTLIB::OGE_F64:

922 case RTLIB::OGE_F128:

923 case RTLIB::OGE_PPCF128:

925 case RTLIB::OLT_F32:

926 case RTLIB::OLT_F64:

927 case RTLIB::OLT_F128:

928 case RTLIB::OLT_PPCF128:

930 case RTLIB::OLE_F32:

931 case RTLIB::OLE_F64:

932 case RTLIB::OLE_F128:

933 case RTLIB::OLE_PPCF128:

935 case RTLIB::OGT_F32:

936 case RTLIB::OGT_F64:

937 case RTLIB::OGT_F128:

938 case RTLIB::OGT_PPCF128:

940 case RTLIB::UO_F32:

941 case RTLIB::UO_F64:

942 case RTLIB::UO_F128:

943 case RTLIB::UO_PPCF128:

945 default:

947 }

948}

949

950

953 : TM(tm),

954 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,

956 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),

957 Libcalls(RuntimeLibcallInfo, STI) {

959

960

966 HasExtractBitsInsn = false;

970 StackPointerRegisterToSaveRestore = 0;

977 MaxBytesForAlignment = 0;

978 MaxAtomicSizeInBitsSupported = 0;

979

980

981

982 MaxDivRemBitWidthSupported = 128;

983

985

986 MinCmpXchgSizeInBits = 0;

987 SupportsUnalignedAtomics = false;

988

990}

991

992

993

995

997

998 memset(OpActions, 0, sizeof(OpActions));

999 memset(LoadExtActions, 0, sizeof(LoadExtActions));

1000 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));

1001 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));

1002 memset(CondCodeActions, 0, sizeof(CondCodeActions));

1004 llvm::fill(TargetDAGCombineArray, 0);

1005

1006

1011

1012

1013

1016 for (MVT VT : {MVT::i2, MVT::i4})

1017 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;

1018 }

1020 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {

1024 }

1025 }

1028 for (MVT VT : {MVT::i2, MVT::i4}) {

1033 }

1034 }

1035

1041 }

1042 }

1043

1044

1046

1053 }

1054

1055

1057

1058

1060 ISD::FMINNUM, ISD::FMAXNUM,

1061 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,

1062 ISD::FMINIMUM, ISD::FMAXIMUM,

1063 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,

1077 ISD::FLOG, ISD::FLOG2,

1078 ISD::FLOG10, ISD::FEXP,

1079 ISD::FEXP2, ISD::FEXP10,

1080 ISD::FFLOOR, ISD::FNEARBYINT,

1081 ISD::FCEIL, ISD::FRINT,

1082 ISD::FTRUNC, ISD::FROUNDEVEN,

1083 ISD::FTAN, ISD::FACOS,

1084 ISD::FASIN, ISD::FATAN,

1085 ISD::FCOSH, ISD::FSINH,

1086 ISD::FTANH, ISD::FATAN2,

1089

1090

1094

1095

1099

1100

1103

1104

1106

1107

1111

1112

1114

1115

1119

1120

1123

1125

1126

1127 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,

1128 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},

1130

1131

1132 if (VT.isVector())

1137 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},

1139

1140

1141#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \

1142 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);

1143#include "llvm/IR/ConstrainedOps.def"

1144

1145

1147

1148

1150 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,

1151 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,

1152 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,

1153 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,

1154 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,

1155 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},

1157

1158

1160

1161

1163

1164

1165#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \

1166 setOperationAction(ISD::SDOPC, VT, Expand);

1167#include "llvm/IR/VPIntrinsics.def"

1168

1169

1171

1174

1175

1179

1181 }

1182

1183

1185

1186

1188

1189

1191

1192

1193

1194

1196 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},

1198

1199

1201 {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Expand);

1202

1203

1204 setOperationAction({ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},

1205 {MVT::f32, MVT::f64, MVT::f128}, LibCall);

1206

1207 setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,

1208 ISD::FSINH, ISD::FTANH, ISD::FATAN2},

1210

1212

1213

1214

1216

1218

1221

1222 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {

1225 }

1227

1228

1229

1231}

1232

1237

1240 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");

1242 return LHSTy;

1244

1245

1247 ShiftVT = MVT::i32;

1249 "ShiftVT is still too small!");

1250 return ShiftVT;

1251}

1252

1255 switch (Op) {

1256 default:

1257 return false;

1262 return true;

1263 }

1264}

1265

1267 unsigned DestAS) const {

1268 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);

1269}

1270

1274

1276 if (EC.isScalable())

1277 CR = CR.umul_sat(*VScaleRange);

1278

1279 if (ZeroIsPoison)

1281

1283 EltWidth = std::min(EltWidth, CR.getActiveBits());

1284 EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8);

1285

1286 return EltWidth;

1287}

1288

1290

1292 JumpIsExpensive = isExpensive;

1293}

1294

1297

1300 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));

1301 MVT NVT = TransformToType[SVT.SimpleTy];

1303

1308 "Promote may not follow Expand or Promote");

1309

1311 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));

1315 }

1316

1317

1321

1324 assert(NVT != VT && "Unable to round integer VT");

1326

1328 return NextStep;

1329

1331 }

1332

1335 }

1336

1337

1340

1341

1344

1345

1346

1347

1349

1350

1355 }

1356

1357

1359

1360

1361

1367 }

1368

1369

1370

1371

1372

1373 EVT OldEltVT = EltVT;

1374 while (true) {

1375

1376

1379

1380

1381

1382

1383

1385 break;

1386

1387

1389

1390 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)

1393 }

1394

1395

1396

1397 EltVT = OldEltVT;

1398 }

1399

1400

1401

1402 while (true) {

1403

1405

1406

1407

1408

1410 break;

1412 if (LargerVector == MVT())

1413 break;

1414

1415

1416 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)

1418 }

1419

1420

1424 }

1425

1428

1429

1433}

1434

1436 unsigned &NumIntermediates,

1437 MVT &RegisterVT,

1439

1442

1443 unsigned NumVectorRegs = 1;

1444

1445

1446

1449 "Splitting or widening of non-power-of-2 MVTs is not implemented.");

1450

1451

1452

1454

1455 NumVectorRegs = EC.getKnownMinValue();

1457 }

1458

1459

1460

1461

1462 while (EC.getKnownMinValue() > 1 &&

1464 EC = EC.divideCoefficientBy(2);

1465 NumVectorRegs <<= 1;

1466 }

1467

1468 NumIntermediates = NumVectorRegs;

1469

1472 NewVT = EltTy;

1473 IntermediateVT = NewVT;

1474

1476

1477

1479

1481 RegisterVT = DestVT;

1482 if (EVT(DestVT).bitsLT(NewVT))

1484

1485

1486

1487 return NumVectorRegs;

1488}

1489

1490

1491

1494 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)

1496 return true;

1497 return false;

1498}

1499

1500

1501

1508

1509

1510

1511

1512

1513

1514

1515

1516

1517

1518

1519

1520

1522 [](MachineOperand &Operand) { return Operand.isFI(); }))

1523 return MBB;

1524

1526

1527

1529

1530 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {

1532 if (!MO.isFI()) {

1533

1534

1535

1536

1537 unsigned TiedTo = i;

1539 TiedTo = MI->findTiedOperandIdx(i);

1540 MIB.add(MO);

1541 if (TiedTo < i)

1543 continue;

1544 }

1545

1546

1547

1549

1550

1552

1553

1554

1555

1556 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");

1557 MIB.addImm(StackMaps::IndirectMemRefOp);

1559 MIB.add(MO);

1561 } else {

1562

1563

1564 MIB.addImm(StackMaps::DirectMemRefOp);

1565 MIB.add(MO);

1567 }

1568

1569 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");

1570

1571

1573

1574

1575

1576 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {

1582 }

1583 }

1585 MI->eraseFromParent();

1586 return MBB;

1587}

1588

1589

1590

1591

1592

1593

1594

1595std::pair<const TargetRegisterClass *, uint8_t>

1597 MVT VT) const {

1599 if (!RC)

1600 return std::make_pair(RC, 0);

1601

1602

1603 BitVector SuperRegRC(TRI->getNumRegClasses());

1606

1607

1609 for (unsigned i : SuperRegRC.set_bits()) {

1611

1612 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))

1613 continue;

1615 continue;

1616 BestRC = SuperRC;

1617 }

1618 return std::make_pair(BestRC, 1);

1619}

1620

1621

1622

1625

1627 NumRegistersForVT[i] = 1;

1629 }

1630

1631 NumRegistersForVT[MVT::isVoid] = 0;

1632

1633

1634 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;

1635 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)

1636 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");

1637

1638

1639

1640 for (unsigned ExpandedReg = LargestIntReg + 1;

1641 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {

1642 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];

1647 }

1648

1649

1650

1651 unsigned LegalIntReg = LargestIntReg;

1652 for (unsigned IntReg = LargestIntReg - 1;

1653 IntReg >= (unsigned)MVT::i1; --IntReg) {

1656 LegalIntReg = IntReg;

1657 } else {

1658 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =

1661 }

1662 }

1663

1664

1667 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];

1668 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;

1669 TransformToType[MVT::ppcf128] = MVT::f64;

1670 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);

1671 } else {

1672 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];

1673 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];

1674 TransformToType[MVT::ppcf128] = MVT::i128;

1675 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);

1676 }

1677 }

1678

1679

1680

1682 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];

1683 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];

1684 TransformToType[MVT::f128] = MVT::i128;

1685 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);

1686 }

1687

1688

1689

1691 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];

1692 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];

1693 TransformToType[MVT::f80] = MVT::i32;

1694 ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);

1695 }

1696

1697

1698

1700 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];

1701 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];

1702 TransformToType[MVT::f64] = MVT::i64;

1703 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);

1704 }

1705

1706

1707

1709 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];

1710 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];

1711 TransformToType[MVT::f32] = MVT::i32;

1712 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);

1713 }

1714

1715

1716

1717

1719

1722

1723 if (!UseFPRegsForHalfType) {

1724 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];

1725 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];

1726 } else {

1727 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];

1728 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];

1729 }

1730 TransformToType[MVT::f16] = MVT::f32;

1731 if (SoftPromoteHalfType) {

1733 } else {

1735 }

1736 }

1737

1738

1739

1740

1742 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];

1743 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];

1744 TransformToType[MVT::bf16] = MVT::f32;

1746 }

1747

1748

1749 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;

1750 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {

1753 continue;

1754

1757 bool IsLegalWiderType = false;

1760 switch (PreferredAction) {

1763 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :

1764 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;

1765

1766

1767 for (unsigned nVT = i + 1;

1770

1771

1774 TransformToType[i] = SVT;

1775 RegisterTypeForVT[i] = SVT;

1776 NumRegistersForVT[i] = 1;

1778 IsLegalWiderType = true;

1779 break;

1780 }

1781 }

1782 if (IsLegalWiderType)

1783 break;

1784 [[fallthrough]];

1785 }

1786

1789

1790 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {

1795 EC.getKnownMinValue() &&

1797 TransformToType[i] = SVT;

1798 RegisterTypeForVT[i] = SVT;

1799 NumRegistersForVT[i] = 1;

1801 IsLegalWiderType = true;

1802 break;

1803 }

1804 }

1805 if (IsLegalWiderType)

1806 break;

1807 } else {

1808

1811 TransformToType[i] = NVT;

1813 RegisterTypeForVT[i] = NVT;

1814 NumRegistersForVT[i] = 1;

1815 break;

1816 }

1817 }

1818 [[fallthrough]];

1819

1822 MVT IntermediateVT;

1823 MVT RegisterVT;

1824 unsigned NumIntermediates;

1826 NumIntermediates, RegisterVT, this);

1827 NumRegistersForVT[i] = NumRegisters;

1828 assert(NumRegistersForVT[i] == NumRegisters &&

1829 "NumRegistersForVT size cannot represent NumRegisters!");

1830 RegisterTypeForVT[i] = RegisterVT;

1831

1833 if (NVT == VT) {

1834

1835 TransformToType[i] = MVT::Other;

1840 else if (EC.getKnownMinValue() > 1)

1842 else

1843 ValueTypeActions.setTypeAction(VT, EC.isScalable()

1846 } else {

1847 TransformToType[i] = NVT;

1849 }

1850 break;

1851 }

1852 default:

1854 }

1855 }

1856

1857

1858

1859

1860

1861

1866 RepRegClassForVT[i] = RRC;

1867 RepRegClassCostForVT[i] = Cost;

1868 }

1869}

1870

1872 EVT VT) const {

1873 assert(!VT.isVector() && "No default SetCC type for vectors!");

1875}

1876

1878 return MVT::i32;

1879}

1880

1881

1882

1883

1884

1885

1886

1887

1888

1890 EVT VT, EVT &IntermediateVT,

1891 unsigned &NumIntermediates,

1892 MVT &RegisterVT) const {

1894

1895

1896

1897

1898

1899

1905 IntermediateVT = RegisterEVT;

1907 NumIntermediates = 1;

1908 return 1;

1909 }

1910 }

1911

1912

1914

1915 unsigned NumVectorRegs = 1;

1916

1917

1918

1921 EVT PartVT = VT;

1922 do {

1923

1925 PartVT = LK.second;

1926 } while (LK.first != TypeLegal);

1927

1930 "Don't know how to legalize this scalable vector type");

1931 }

1932

1933 NumIntermediates =

1936 IntermediateVT = PartVT;

1938 return NumIntermediates;

1939 }

1940

1941

1942

1946 }

1947

1948

1949

1953 NumVectorRegs <<= 1;

1954 }

1955

1956 NumIntermediates = NumVectorRegs;

1957

1960 NewVT = EltTy;

1961 IntermediateVT = NewVT;

1962

1964 RegisterVT = DestVT;

1965

1966 if (EVT(DestVT).bitsLT(NewVT)) {

1968

1971 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());

1972 }

1973

1974

1975

1976 return NumVectorRegs;

1977}

1978

1984

1985

1986

1987

1988

1989 const bool OptForSize =

1993

1994

1995

1996 return (OptForSize || Range <= MaxJumpTableSize) &&

1997 (NumCases * 100 >= Range * MinDensity);

1998}

1999

2001 EVT ConditionVT) const {

2003}

2004

2005

2006

2007

2008

2010 AttributeList attr,

2015 unsigned NumValues = Types.size();

2016 if (NumValues == 0) return;

2017

2018 for (Type *Ty : Types) {

2021

2022 if (attr.hasRetAttr(Attribute::SExt))

2024 else if (attr.hasRetAttr(Attribute::ZExt))

2026

2029

2030 unsigned NumParts =

2032 MVT PartVT =

2034

2035

2037 if (attr.hasRetAttr(Attribute::InReg))

2038 Flags.setInReg();

2039

2040

2041 if (attr.hasRetAttr(Attribute::SExt))

2042 Flags.setSExt();

2043 else if (attr.hasRetAttr(Attribute::ZExt))

2044 Flags.setZExt();

2045

2046 for (unsigned i = 0; i < NumParts; ++i)

2048 }

2049}

2050

2053 return DL.getABITypeAlign(Ty);

2054}

2055

2059

2060

2061

2062

2063

2065 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {

2066

2067 if (Fast != nullptr)

2069 return true;

2070 }

2071

2072

2074}

2075

2082

2085 unsigned AddrSpace, Align Alignment,

2087 unsigned *Fast) const {

2089 Flags, Fast);

2090}

2091

2095 unsigned *Fast) const {

2098}

2099

2103 unsigned *Fast) const {

2107}

2108

2109

2110

2111

2112

2114 enum InstructionOpcodes {

2115#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,

2116#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM

2117#include "llvm/IR/Instruction.def"

2118 };

2119 switch (static_cast<InstructionOpcodes>(Opcode)) {

2120 case Ret: return 0;

2121 case Br: return 0;

2122 case Switch: return 0;

2123 case IndirectBr: return 0;

2124 case Invoke: return 0;

2125 case CallBr: return 0;

2126 case Resume: return 0;

2127 case Unreachable: return 0;

2128 case CleanupRet: return 0;

2129 case CatchRet: return 0;

2130 case CatchPad: return 0;

2131 case CatchSwitch: return 0;

2132 case CleanupPad: return 0;

2133 case FNeg: return ISD::FNEG;

2152 case Alloca: return 0;

2153 case Load: return ISD::LOAD;

2154 case Store: return ISD::STORE;

2155 case GetElementPtr: return 0;

2156 case Fence: return 0;

2157 case AtomicCmpXchg: return 0;

2158 case AtomicRMW: return 0;

2167 case FPExt: return ISD::FP_EXTEND;

2168 case PtrToAddr: return ISD::BITCAST;

2169 case PtrToInt: return ISD::BITCAST;

2170 case IntToPtr: return ISD::BITCAST;

2171 case BitCast: return ISD::BITCAST;

2172 case AddrSpaceCast: return ISD::ADDRSPACECAST;

2175 case PHI: return 0;

2176 case Call: return 0;

2178 case UserOp1: return 0;

2179 case UserOp2: return 0;

2180 case VAArg: return 0;

2186 case LandingPad: return 0;

2188 }

2189

2191}

2192

2194 switch (ID) {

2195 case Intrinsic::exp:

2196 return ISD::FEXP;

2197 case Intrinsic::exp2:

2198 return ISD::FEXP2;

2199 case Intrinsic:🪵

2200 return ISD::FLOG;

2201 default:

2203 }

2204}

2205

2208 bool UseTLS) const {

2209

2210

2212 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";

2213 auto UnsafeStackPtr =

2215

2217 PointerType *StackPtrTy = DL.getAllocaPtrType(M->getContext());

2218

2219 if (!UnsafeStackPtr) {

2223

2224

2225

2228 UnsafeStackPtrVar, nullptr, TLSModel);

2229 } else {

2230

2231

2232

2233 if (UnsafeStackPtr->getValueType() != StackPtrTy)

2235 if (UseTLS != UnsafeStackPtr->isThreadLocal())

2237 (UseTLS ? "" : "not ") + "be thread-local");

2238 }

2239 return UnsafeStackPtr;

2240}

2241

2244

2245

2246 if (!TM.getTargetTriple().isAndroid())

2248

2251

2252 const char *SafestackPointerAddressName =

2254 if (!SafestackPointerAddressName) {

2255 M->getContext().emitError(

2256 "no libcall available for safestack pointer address");

2258 }

2259

2260

2261

2263 M->getOrInsertFunction(SafestackPointerAddressName, PtrTy);

2265}

2266

2267

2268

2269

2270

2271

2272

2276

2277

2278

2279

2281 return false;

2282

2283

2284 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)

2285 return false;

2286

2287

2289 return false;

2290

2291

2292 switch (AM.Scale) {

2293 case 0:

2294 break;

2295 case 1:

2297 return false;

2298

2299 break;

2300 case 2:

2302 return false;

2303

2304 break;

2305 default:

2306 return false;

2307 }

2308

2309 return true;

2310}

2311

2312

2313

2314

2315

2316

2317

2319 RTLIB::LibcallImpl GuardLocalImpl = getLibcallImpl(RTLIB::STACK_CHECK_GUARD);

2320 if (GuardLocalImpl != RTLIB::impl___guard_local)

2321 return nullptr;

2322

2326 PointerType::get(M.getContext(), DL.getDefaultGlobalsAddressSpace());

2330 return G;

2331}

2332

2333

2334

2336 RTLIB::LibcallImpl StackGuardImpl = getLibcallImpl(RTLIB::STACK_CHECK_GUARD);

2337 if (StackGuardImpl == RTLIB::Unsupported)

2338 return;

2339

2341 M.getOrInsertGlobal(

2343 auto *GV = new GlobalVariable(M, PointerType::getUnqual(M.getContext()),

2344 false, GlobalVariable::ExternalLinkage,

2345 nullptr, StackGuardVarName);

2346

2347

2348 if (M.getDirectAccessExternalData() &&

2349 !TM.getTargetTriple().isOSCygMing() &&

2350 !(TM.getTargetTriple().isPPC64() &&

2351 TM.getTargetTriple().isOSFreeBSD()) &&

2352 (!TM.getTargetTriple().isOSDarwin() ||

2353 TM.getRelocationModel() == Reloc::Static))

2354 GV->setDSOLocal(true);

2355

2356 return GV;

2357 });

2358}

2359

2360

2361

2363 RTLIB::LibcallImpl GuardVarImpl = getLibcallImpl(RTLIB::STACK_CHECK_GUARD);

2364 if (GuardVarImpl == RTLIB::Unsupported)

2365 return nullptr;

2367}

2368

2370

2371 RTLIB::LibcallImpl SecurityCheckCookieLibcall =

2373 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)

2374 return M.getFunction(getLibcallImplName(SecurityCheckCookieLibcall));

2375 return nullptr;

2376}

2377

2381

2385

2389

2393

2397

2401

2403 return MinimumBitTestCmps;

2404}

2405

2407 MinimumBitTestCmps = Val;

2408}

2409

2411 if (TM.Options.LoopAlignment)

2412 return Align(TM.Options.LoopAlignment);

2413 return PrefLoopAlignment;

2414}

2415

2418 return MaxBytesForAlignment;

2419}

2420

2421

2422

2423

2424

2425

2426

2429 return F.getFnAttribute("reciprocal-estimates").getValueAsString();

2430}

2431

2432

2433

2434

2435

2437 std::string Name = VT.isVector() ? "vec-" : "";

2438

2439 Name += IsSqrt ? "sqrt" : "div";

2440

2441

2443 Name += "d";

2445 Name += "h";

2446 } else {

2448 "Unexpected FP type for reciprocal estimate");

2449 Name += "f";

2450 }

2451

2452 return Name;

2453}

2454

2455

2456

2457

2460 const char RefStepToken = ':';

2461 Position = In.find(RefStepToken);

2463 return false;

2464

2465 StringRef RefStepString = In.substr(Position + 1);

2466

2467

2468 if (RefStepString.size() == 1) {

2469 char RefStepChar = RefStepString[0];

2470 if (isDigit(RefStepChar)) {

2471 Value = RefStepChar - '0';

2472 return true;

2473 }

2474 }

2476}

2477

2478

2479

2480

2482 if (Override.empty())

2484

2486 Override.split(OverrideVector, ',');

2487 unsigned NumArgs = OverrideVector.size();

2488

2489

2490 if (NumArgs == 1) {

2491

2492

2493 size_t RefPos;

2496

2497 Override = Override.substr(0, RefPos);

2498 }

2499

2500

2501 if (Override == "all")

2503

2504

2505 if (Override == "none")

2507

2508

2509 if (Override == "default")

2511 }

2512

2513

2515 std::string VTNameNoSize = VTName;

2516 VTNameNoSize.pop_back();

2517 static const char DisabledPrefix = '!';

2518

2519 for (StringRef RecipType : OverrideVector) {

2520 size_t RefPos;

2523 RecipType = RecipType.substr(0, RefPos);

2524

2525

2526 bool IsDisabled = RecipType[0] == DisabledPrefix;

2527 if (IsDisabled)

2528 RecipType = RecipType.substr(1);

2529

2530 if (RecipType == VTName || RecipType == VTNameNoSize)

2533 }

2534

2536}

2537

2538

2539

2540

2542 if (Override.empty())

2544

2546 Override.split(OverrideVector, ',');

2547 unsigned NumArgs = OverrideVector.size();

2548

2549

2550 if (NumArgs == 1) {

2551

2552

2553 size_t RefPos;

2557

2558

2559 Override = Override.substr(0, RefPos);

2560 assert(Override != "none" &&

2561 "Disabled reciprocals, but specifed refinement steps?");

2562

2563

2564 if (Override == "all" || Override == "default")

2565 return RefSteps;

2566 }

2567

2568

2570 std::string VTNameNoSize = VTName;

2571 VTNameNoSize.pop_back();

2572

2573 for (StringRef RecipType : OverrideVector) {

2574 size_t RefPos;

2577 continue;

2578

2579 RecipType = RecipType.substr(0, RefPos);

2580 if (RecipType == VTName || RecipType == VTNameNoSize)

2581 return RefSteps;

2582 }

2583

2585}

2586

2591

2596

2601

2606

2610

2611

2614 return false;

2615

2616

2617

2619 return true;

2620

2622

2623

2624

2627 return false;

2628

2629 unsigned Fast = 0;

2631 MMO, &Fast) &&

2633}

2634

2638

2645

2646 if (LI.hasMetadata(LLVMContext::MD_nontemporal))

2648

2649 if (LI.hasMetadata(LLVMContext::MD_invariant_load))

2651

2654 nullptr, LibInfo))

2656

2658 return Flags;

2659}

2660

2665

2666 if (SI.isVolatile())

2668

2669 if (SI.hasMetadata(LLVMContext::MD_nontemporal))

2671

2672

2674 return Flags;

2675}

2676

2681

2683 if (RMW->isVolatile())

2686 if (CmpX->isVolatile())

2688 } else

2690

2691

2693 return Flags;

2694}

2695

2700

2701 switch (IntrinID) {

2702 default:

2703 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "

2704 "for it, but support must be explicitly enabled");

2705 case Intrinsic::vp_load:

2706 case Intrinsic::vp_gather:

2707 case Intrinsic::experimental_vp_strided_load:

2709 break;

2710 case Intrinsic::vp_store:

2711 case Intrinsic::vp_scatter:

2712 case Intrinsic::experimental_vp_strided_store:

2714 break;

2715 }

2716

2717 if (VPIntrin.hasMetadata(LLVMContext::MD_nontemporal))

2719

2721 return Flags;

2722}

2723

2728 return Builder.CreateFence(Ord);

2729 else

2730 return nullptr;

2731}

2732

2737 return Builder.CreateFence(Ord);

2738 else

2739 return nullptr;

2740}

2741

2742

2743

2744

2745

2748 auto &MF = *MI.getMF();

2749 auto &MRI = MF.getRegInfo();

2750

2751

2752

2753

2754

2755

2756 auto maxUses = [](unsigned RematCost) {

2757

2758 if (RematCost == 1)

2759 return std::numeric_limits::max();

2760 if (RematCost == 2)

2761 return 2U;

2762

2763

2764 if (RematCost > 2)

2765 return 1U;

2767 };

2768

2769 switch (MI.getOpcode()) {

2770 default:

2771 return false;

2772

2773

2774 case TargetOpcode::G_CONSTANT:

2775 case TargetOpcode::G_FCONSTANT:

2776 case TargetOpcode::G_FRAME_INDEX:

2777 case TargetOpcode::G_INTTOPTR:

2778 return true;

2779 case TargetOpcode::G_GLOBAL_VALUE: {

2780 unsigned RematCost = TTI->getGISelRematGlobalCost();

2781 Register Reg = MI.getOperand(0).getReg();

2782 unsigned MaxUses = maxUses(RematCost);

2783 if (MaxUses == UINT_MAX)

2784 return true;

2785 return MRI.hasAtMostUserInstrs(Reg, MaxUses);

2786 }

2787 }

2788}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

AMDGPU Register Bank Select

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file contains the simple types necessary to represent the attributes associated with functions a...

This file implements the BitVector class.

This file defines the DenseMap class.

Module.h This file contains the declarations for the Module class.

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

This file defines the SmallVector class.

static cl::opt< unsigned > MinimumBitTestCmpsOverride("min-bit-test-cmps", cl::init(2), cl::Hidden, cl::desc("Set minimum of largest number of comparisons " "to use bit test for switch."))

static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)

#define OP_TO_LIBCALL(Name, Enum)

static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))

static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)

static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)

Return the character position and value (a single numeric character) of a customized refinement opera...

Definition TargetLoweringBase.cpp:2458

static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))

static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))

Minimum jump table density for normal functions.

static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)

Definition TargetLoweringBase.cpp:1435

static std::string getReciprocalOpName(bool IsSqrt, EVT VT)

Construct a string for the given reciprocal operation of the given type.

Definition TargetLoweringBase.cpp:2436

static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return the customized refinement step count for this operation on the...

Definition TargetLoweringBase.cpp:2541

static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...

Definition TargetLoweringBase.cpp:2481

static StringRef getRecipEstimateForFunc(MachineFunction &MF)

Get the reciprocal estimate attribute string for a function that will override the target defaults.

Definition TargetLoweringBase.cpp:2427

static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))

Minimum jump table density for -Os or -Oz functions.

This file describes how to lower LLVM code to machine code.

This pass exposes codegen information to IR-level passes.

Class for arbitrary precision integers.

A cache of @llvm.assume calls within a function.

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

const Function * getParent() const

Return the enclosing method, or null if none.

void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

setBitsInMask - Add '1' bits from Mask to this vector.

iterator_range< const_set_bits_iterator > set_bits() const

BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...

This class represents a range of values.

LLVM_ABI unsigned getActiveBits() const

Compute the maximal number of active bits needed to represent every value in this range.

LLVM_ABI ConstantRange umul_sat(const ConstantRange &Other) const

Perform an unsigned saturating multiplication of two constant ranges.

LLVM_ABI ConstantRange subtract(const APInt &CI) const

Subtract the specified constant from the endpoints of this constant range.

A parsed version of the target data layout string in and methods for querying it.

LLVM_ABI unsigned getPointerSize(unsigned AS=0) const

The pointer representation size in bytes, rounded up to a whole number of bytes.

static constexpr ElementCount getScalable(ScalarTy MinVal)

static constexpr ElementCount getFixed(ScalarTy MinVal)

constexpr bool isScalar() const

Exactly one element.

A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...

Module * getParent()

Get the module that this global value is contained inside of...

@ HiddenVisibility

The GV is hidden.

@ ExternalLinkage

Externally visible function.

Common base class shared among various IRBuilders.

BasicBlock * GetInsertBlock() const

CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args={}, const Twine &Name="", MDNode *FPMathTag=nullptr)

LLVM_ABI bool hasAtomicStore() const LLVM_READONLY

Return true if this atomic instruction stores to memory.

bool hasMetadata() const

Return true if this instruction has any metadata attached to it.

@ MAX_INT_BITS

Maximum number of bits that can be specified.

Intrinsic::ID getIntrinsicID() const

Return the intrinsic ID of this intrinsic.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

Value * getPointerOperand()

bool isVolatile() const

Return true if this is a load from a volatile memory location.

Align getAlign() const

Return the alignment of the access that is being performed.

uint64_t getScalarSizeInBits() const

bool isVector() const

Return true if this is a vector value type.

bool isScalableVector() const

Return true if this is a vector value type where the runtime length is machine dependent.

static auto all_valuetypes()

SimpleValueType Iteration.

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

ElementCount getVectorElementCount() const

bool isScalarInteger() const

Return true if this is an integer, not including vectors.

static MVT getVectorVT(MVT VT, unsigned NumElements)

MVT getVectorElementType() const

bool isValid() const

Return true if this is a valid simple valuetype.

static MVT getIntegerVT(unsigned BitWidth)

static auto fp_valuetypes()

MVT getPow2VectorType() const

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const

Representation of each machine instruction.

unsigned getNumOperands() const

Retuns the total number of operands.

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

LLVM_ABI void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

A description of a memory reference used in the backend.

unsigned getAddrSpace() const

Flags

Flags values. These may be or'd together.

@ MOVolatile

The memory access is volatile.

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

@ MOLoad

The memory access reads data.

@ MONonTemporal

The memory access is non-temporal.

@ MOInvariant

The memory access always returns the same value (or traps).

@ MOStore

The memory access writes data.

Flags getFlags() const

Return the raw flags of the source value,.

LLVM_ABI Align getAlign() const

Return the minimum known alignment in bytes of the actual memory reference.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

bool isFI() const

isFI - Tests if this is a MO_FrameIndex operand.

LLVM_ABI void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

A Module instance is used to store all the information related to an LLVM module.

Class to represent pointers.

static PointerType * getUnqual(Type *ElementType)

This constructs a pointer to an object of the specified type in the default address space (address sp...

static LLVM_ABI PointerType * get(Type *ElementType, unsigned AddressSpace)

This constructs a pointer to an object of the specified type in a numbered address space.

static LLVM_ABI PoisonValue * get(Type *T)

Static factory methods - Return an 'poison' object of the specified type.

Analysis providing profile information.

Wrapper class representing virtual and physical registers.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

const DataLayout & getDataLayout() const

LLVMContext * getContext() const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

static constexpr size_t npos

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

constexpr bool empty() const

empty - Check if the string is empty.

constexpr size_t size() const

size - Get the string size.

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

Provides information about what library functions are available for the current target.

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...

virtual Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const

Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parame...

Definition TargetLoweringBase.cpp:2051

int InstructionOpcodeToISD(unsigned Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition TargetLoweringBase.cpp:2113

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

virtual void finalizeLowering(MachineFunction &MF) const

Execute target specific actions to finalize target lowering.

Definition TargetLoweringBase.cpp:2635

void initActions()

Initialize all of the actions to default values.

Definition TargetLoweringBase.cpp:996

bool PredictableSelectIsExpensive

Tells the code generator that select is more expensive than a branch if the branch is usually predict...

EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

Return the EVT corresponding to this LLVM type.

void setMinimumBitTestCmps(unsigned Val)

Set the minimum of largest of number of comparisons to generate BitTest.

Definition TargetLoweringBase.cpp:2406

unsigned MaxStoresPerMemcpyOptSize

Likewise for functions with the OptSize attribute.

MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...

Definition TargetLoweringBase.cpp:1503

virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const

Returns the target-specific address of the unsafe stack pointer.

Definition TargetLoweringBase.cpp:2243

int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...

Definition TargetLoweringBase.cpp:2587

virtual bool canOpTrap(unsigned Op, EVT VT) const

Returns true if the operation can trap for the value type.

Definition TargetLoweringBase.cpp:1253

virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const

Check whether or not MI needs to be moved close to its uses.

Definition TargetLoweringBase.cpp:2746

virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const

Return the maximum amount of bytes allowed to be emitted when padding for alignment.

Definition TargetLoweringBase.cpp:2416

void setMaximumJumpTableSize(unsigned)

Indicate the maximum number of entries in jump tables.

Definition TargetLoweringBase.cpp:2394

virtual unsigned getMinimumJumpTableEntries() const

Return lower limit for number of blocks in a jump table.

Definition TargetLoweringBase.cpp:2378

const TargetMachine & getTargetMachine() const

unsigned MaxLoadsPerMemcmp

Specify maximum number of load instructions per memcmp call.

virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain targets require unusual breakdowns of certain types.

virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...

unsigned MaxGluedStoresPerMemcpy

Specify max number of store instructions to glue in inlined memcpy.

virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

@ TypeScalarizeScalableVector

virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...

Definition TargetLoweringBase.cpp:1979

void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked load does or does not work with the specified type and ind...

virtual Value * getSDagStackGuard(const Module &M) const

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...

Definition TargetLoweringBase.cpp:2362

unsigned getMinimumBitTestCmps() const

Retuen the minimum of largest number of comparisons in BitTest.

Definition TargetLoweringBase.cpp:2402

virtual bool useFPRegsForHalfType() const

virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...

Definition TargetLoweringBase.cpp:2607

void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed load does or does not work with the specified type and indicate w...

virtual bool softPromoteHalfType() const

unsigned getMaximumJumpTableSize() const

Return upper limit for number of entries in a jump table.

Definition TargetLoweringBase.cpp:2390

virtual MVT::SimpleValueType getCmpLibcallReturnType() const

Return the ValueType for comparison libcalls.

Definition TargetLoweringBase.cpp:1877

unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const

Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...

Definition TargetLoweringBase.cpp:1271

bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const

Return true if the value types that can be represented by the specified register class are all legal.

Definition TargetLoweringBase.cpp:1492

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Let target indicate that an extending atomic load of the specified type is legal.

Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const

Definition TargetLoweringBase.cpp:2207

Function * getSSPStackGuardCheck(const Module &M) const

If the target has a standard stack protection check function that performs validation and error handl...

Definition TargetLoweringBase.cpp:2369

MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const

Definition TargetLoweringBase.cpp:2678

virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const

Determine if the target supports unaligned memory accesses.

unsigned MaxStoresPerMemsetOptSize

Likewise for functions with the OptSize attribute.

EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const

Returns the type for the shift amount of a shift opcode.

Definition TargetLoweringBase.cpp:1238

unsigned MaxStoresPerMemmove

Specify maximum number of store instructions per memmove call.

virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const

Return the preferred loop alignment.

Definition TargetLoweringBase.cpp:2410

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition TargetLoweringBase.cpp:1623

MachineMemOperand::Flags getVPIntrinsicMemOperandFlags(const VPIntrinsic &VPIntrin) const

Definition TargetLoweringBase.cpp:2696

int getDivRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a division of the given type based on the function's attributes.

Definition TargetLoweringBase.cpp:2602

virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const

Return the ValueType of the result of SETCC operations.

Definition TargetLoweringBase.cpp:1871

MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const

Definition TargetLoweringBase.cpp:2639

virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const

For types supported by the target, this is an identity function.

unsigned MaxStoresPerMemmoveOptSize

Likewise for functions with the OptSize attribute.

virtual Value * getIRStackGuard(IRBuilderBase &IRB) const

If the target has a standard location for the stack protector guard, returns the address of that loca...

Definition TargetLoweringBase.cpp:2318

virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const

Returns preferred type for switch condition.

Definition TargetLoweringBase.cpp:2000

bool isTypeLegal(EVT VT) const

Return true if the target has native support for the specified value type.

bool EnableExtLdPromotion

int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...

Definition TargetLoweringBase.cpp:2592

void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed store does or does not work with the specified type and indicate ...

virtual bool isJumpTableRelative() const

Definition TargetLoweringBase.cpp:2398

virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition TargetLoweringBase.cpp:1233

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

Definition TargetLoweringBase.cpp:1266

ISD::CondCode getSoftFloatCmpLibcallPredicate(RTLIB::LibcallImpl Call) const

Get the comparison predicate that's to be used to test the result of the comparison libcall against z...

Definition TargetLoweringBase.cpp:875

void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked store does or does not work with the specified type and in...

TargetLoweringBase(const TargetMachine &TM, const TargetSubtargetInfo &STI)

NOTE: The TargetMachine owns TLOF.

Definition TargetLoweringBase.cpp:951

unsigned MaxStoresPerMemset

Specify maximum number of store instructions per memset call.

void setMinimumJumpTableEntries(unsigned Val)

Indicate the minimum number of blocks to generate jump tables.

Definition TargetLoweringBase.cpp:2382

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

@ UndefinedBooleanContent

virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

Return true if the target supports a memory access of this type for the given address space and align...

Definition TargetLoweringBase.cpp:2083

unsigned MaxLoadsPerMemcmpOptSize

Likewise for functions with the OptSize attribute.

MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const

Definition TargetLoweringBase.cpp:2662

virtual ~TargetLoweringBase()

void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...

unsigned getMinimumJumpTableDensity(bool OptForSize) const

Return lower limit of the density in a jump table.

Definition TargetLoweringBase.cpp:2386

virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const

Return the largest legal super-reg register class of the register class for the specified type and it...

Definition TargetLoweringBase.cpp:1596

RTLIB::LibcallImpl getLibcallImpl(RTLIB::Libcall Call) const

Get the libcall impl routine name for the specified libcall.

static StringRef getLibcallImplName(RTLIB::LibcallImpl Call)

Get the libcall routine name for the specified libcall implementation.

LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const

Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...

Definition TargetLoweringBase.cpp:1296

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

unsigned GatherAllAliasesMaxDepth

Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...

int IntrinsicIDToISD(Intrinsic::ID ID) const

Get the ISD node that corresponds to the Intrinsic ID.

Definition TargetLoweringBase.cpp:2193

LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...

int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a square root of the given type based on the function's attribut...

Definition TargetLoweringBase.cpp:2597

const char * getLibcallName(RTLIB::Libcall Call) const

Get the libcall routine name for the specified libcall.

bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

This function returns true if the memory access is aligned or if the target allows this specific unal...

Definition TargetLoweringBase.cpp:2056

virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Definition TargetLoweringBase.cpp:2733

virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Inserts in the IR a target-specific intrinsic specifying a fence.

Definition TargetLoweringBase.cpp:2724

unsigned MaxStoresPerMemcpy

Specify maximum number of store instructions per memcpy call.

MVT getRegisterType(MVT VT) const

Return the type of registers that this ValueType will eventually require.

virtual void insertSSPDeclarations(Module &M) const

Inserts necessary declarations for SSP (stack protection) purpose.

Definition TargetLoweringBase.cpp:2335

void setJumpIsExpensive(bool isExpensive=true)

Tells the code generator not to expand logic operations on comparison predicates into separate sequen...

Definition TargetLoweringBase.cpp:1289

LegalizeAction getOperationAction(unsigned Op, EVT VT) const

Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...

MVT getTypeToPromoteTo(unsigned Op, MVT VT) const

If the action for this operation is to promote, this method returns the ValueType to promote to.

virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

Definition TargetLoweringBase.cpp:2273

unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

Vector types are broken down into some number of legal first class types.

Definition TargetLoweringBase.cpp:1889

std::pair< LegalizeTypeAction, EVT > LegalizeKind

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

Primary interface to the complete machine description for the target machine.

bool isPositionIndependent() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM_ABI unsigned getScalarSizeInBits() const LLVM_READONLY

If this is a vector type, return the getPrimitiveSizeInBits value for the element type.

This is the common base class for vector predication intrinsics.

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

constexpr LeafTy coefficientNextPowerOf2() const

constexpr bool isScalable() const

Returns whether the quantity is scaled by a runtime quantity (vscale).

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const

We do not provide the '/' operator here because division for polynomial types does not work in the sa...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ MERGE_VALUES

MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...

@ DELETED_NODE

DELETED_NODE - This is an illegal value that is used to catch errors.

@ LOOP_DEPENDENCE_RAW_MASK

@ FGETSIGN

INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...

@ SMULFIX

RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...

@ ADDC

Carry-setting nodes for multiple precision addition and subtraction.

@ FMAD

FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.

@ ADD

Simple integer binary arithmetic operators.

@ SMULFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ CONCAT_VECTORS

CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...

@ FADD

Simple binary floating point operators.

@ ABS

ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.

@ SIGN_EXTEND_VECTOR_INREG

SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...

@ FMULADD

FMULADD - Performs a * b + c, with, or without, intermediate rounding.

@ SDIVFIX

RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

@ SIGN_EXTEND

Conversion operators.

@ AVGCEILS

AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...

@ CTTZ_ZERO_UNDEF

Bit counting operators with an undefined result for zero inputs.

@ SETCCCARRY

Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...

@ SSUBO

Same for subtraction.

@ FCANONICALIZE

Returns platform specific canonical encoding of a floating point number.

@ IS_FPCLASS

Performs a check of floating point class property, defined by IEEE-754.

@ SSUBSAT

RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ SPLAT_VECTOR

SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.

@ SADDO

RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.

@ SHL

Shift and rotation operations.

@ VECTOR_SHUFFLE

VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SSHLSAT

RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.

@ SMULO

Same for multiplication.

@ ANY_EXTEND_VECTOR_INREG

ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ SDIVFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ UADDO_CARRY

Carry-using nodes for multiple precision addition and subtraction.

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ SCMP

[US]CMP - 3-way comparison of signed or unsigned integers.

@ AVGFLOORS

AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...

@ ADDE

Carry-using nodes for multiple precision addition and subtraction.

@ FREEZE

FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

@ VECTOR_SPLICE

VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...

@ FP_ROUND

X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...

@ VECTOR_COMPRESS

VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....

@ ZERO_EXTEND_VECTOR_INREG

ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...

@ FP_TO_SINT_SAT

FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

@ SADDSAT

RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...

@ TRUNCATE_SSAT_S

TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand [SU] located in middle, prefix for SAT means i...

@ ABDS

ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...

@ SADDO_CARRY

Carry-using overflow-aware nodes for multiple precision addition and subtraction.

@ LOOP_DEPENDENCE_WAR_MASK

Set rounding mode.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

static const int LAST_INDEXED_MODE

LLVM_ABI Libcall getPOWI(EVT RetVT)

getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:518

LLVM_ABI Libcall getSINTTOFP(EVT OpVT, EVT RetVT)

getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:424

LLVM_ABI Libcall getUREM(EVT VT)

Definition TargetLoweringBase.cpp:203

LLVM_ABI Libcall getSHL(EVT VT)

Definition TargetLoweringBase.cpp:106

LLVM_ABI Libcall getSYNC(unsigned Opc, MVT VT)

Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:786

LLVM_ABI Libcall getLDEXP(EVT RetVT)

getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:527

LLVM_ABI Libcall getUINTTOFP(EVT OpVT, EVT RetVT)

getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:472

LLVM_ABI Libcall getFREXP(EVT RetVT)

getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:532

LLVM_ABI Libcall getREM(EVT VT)

Definition TargetLoweringBase.cpp:596

LLVM_ABI Libcall getSINCOSPI(EVT RetVT)

getSINCOSPI - Return the SINCOSPI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:568

LLVM_ABI Libcall getSDIV(EVT VT)

Definition TargetLoweringBase.cpp:167

LLVM_ABI Libcall getSRL(EVT VT)

Definition TargetLoweringBase.cpp:119

LLVM_ABI Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Definition TargetLoweringBase.cpp:824

LLVM_ABI Libcall getSRA(EVT VT)

Definition TargetLoweringBase.cpp:132

LLVM_ABI Libcall getUDIV(EVT VT)

Definition TargetLoweringBase.cpp:179

LLVM_ABI Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)

GetFPLibCall - Helper to return the right libcall for the given floating point type,...

LLVM_ABI Libcall getFPTOUINT(EVT OpVT, EVT RetVT)

getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:375

LLVM_ABI Libcall getLLROUND(EVT VT)

Definition TargetLoweringBase.cpp:656

LLVM_ABI Libcall getCOS(EVT RetVT)

Return the COS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:541

LLVM_ABI Libcall getLROUND(EVT VT)

Definition TargetLoweringBase.cpp:641

LLVM_ABI Libcall getMODF(EVT VT)

getMODF - Return the MODF_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:618

LLVM_ABI Libcall getFPTOSINT(EVT OpVT, EVT RetVT)

getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:326

LLVM_ABI Libcall getLRINT(EVT RetVT)

Definition TargetLoweringBase.cpp:671

LLVM_ABI Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)

Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...

Definition TargetLoweringBase.cpp:744

LLVM_ABI Libcall getLLRINT(EVT RetVT)

Definition TargetLoweringBase.cpp:685

LLVM_ABI Libcall getFPEXT(EVT OpVT, EVT RetVT)

getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:244

LLVM_ABI Libcall getFPROUND(EVT OpVT, EVT RetVT)

getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:279

LLVM_ABI Libcall getSREM(EVT VT)

Definition TargetLoweringBase.cpp:191

LLVM_ABI Libcall getSIN(EVT RetVT)

Return the SIN_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:537

LLVM_ABI Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Definition TargetLoweringBase.cpp:858

LLVM_ABI Libcall getSINCOS_STRET(EVT RetVT)

Return the SINCOS_STRET_ value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:591

LLVM_ABI Libcall getPOW(EVT RetVT)

getPOW - Return the POW_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:523

LLVM_ABI Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)

Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...

Definition TargetLoweringBase.cpp:699

LLVM_ABI Libcall getMUL(EVT VT)

Definition TargetLoweringBase.cpp:145

LLVM_ABI Libcall getCTPOP(EVT VT)

Definition TargetLoweringBase.cpp:215

LLVM_ABI Libcall getSINCOS(EVT RetVT)

getSINCOS - Return the SINCOS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition TargetLoweringBase.cpp:545

LLVM_ABI Libcall getMULO(EVT VT)

Definition TargetLoweringBase.cpp:157

LLVM_ABI Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...

Definition TargetLoweringBase.cpp:841

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

unsigned Log2_32_Ceil(uint32_t Value)

Return the ceil log base 2 of the specified value, 32 if the value is zero.

void fill(R &&Range, T &&Value)

Provide wrappers to std::fill which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)

Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...

Definition TargetLoweringBase.cpp:2009

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

auto enum_seq(EnumT Begin, EnumT End)

Iterate over an enum type from Begin up to - but not including - End.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)

Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.

LLVM_ABI bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum

T bit_ceil(T Value)

Returns the smallest integral power of two no smaller than Value if Value is nonzero.

void ComputeValueTypes(const DataLayout &DL, Type *Ty, SmallVectorImpl< Type * > &Types, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())

Given an LLVM IR type, compute non-aggregate subtypes.

bool isReleaseOrStronger(AtomicOrdering AO)

auto dyn_cast_or_null(const Y &Val)

constexpr bool has_single_bit(T Value) noexcept

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

bool isDigit(char C)

Checks if character C is one of the 10 decimal digits.

AtomicOrdering

Atomic ordering for LLVM's memory model.

LLVM_ABI EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)

constexpr T divideCeil(U Numerator, V Denominator)

Returns the integer ceil(Numerator / Denominator).

@ Mul

Product of integers.

@ Xor

Bitwise or logical XOR of integers.

@ Sub

Subtraction of integers.

DWARFExpression::Operation Op

bool isAcquireOrStronger(AtomicOrdering AO)

This struct is a compact representation of a valid (non-zero power of two) alignment.

EVT getPow2VectorType(LLVMContext &Context) const

Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

ElementCount getVectorElementCount() const

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

bool isPow2VectorType() const

Returns true if the given vector is a power of 2.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)

Returns the EVT that represents an integer with the given number of bits.

bool isFixedLengthVector() const

EVT getRoundIntegerType(LLVMContext &Context) const

Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...

bool isVector() const

Return true if this is a vector value type.

EVT getScalarType() const

If this is a vector type, return the element type, otherwise return this.

LLVM_ABI Type * getTypeForEVT(LLVMContext &Context) const

This method returns an LLVM type corresponding to the specified EVT.

EVT getVectorElementType() const

Given a vector type, return the type of each element.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

bool isZeroSized() const

Test if the given EVT has zero size, this will fail if called on a scalable type.

EVT getHalfNumVectorElementsVT(LLVMContext &Context) const

bool isInteger() const

Return true if this is an integer or a vector integer type.

OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

static RTLIB::Libcall getLibcallFromImpl(RTLIB::LibcallImpl Impl)

Return the libcall provided by Impl.

This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...