LLVM: include/llvm/CodeGen/TargetRegisterInfo.h Source File (original) (raw)
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15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
31#include
32#include
33
34namespace llvm {
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46public:
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74 unsigned getID() const { return MC->getID(); }
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82 unsigned getNumRegs() const { return MC->getNumRegs(); }
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90 return MC->getRegister(i);
91 }
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98 if (.isPhysical())
99 return false;
100 return MC->contains(Reg.asMCReg());
101 }
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108 return false;
110 }
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119 return MC->getCopyCost() == std::numeric_limits<uint8_t>::max();
120 }
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137 unsigned ID = RC->getID();
139 }
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208 bool Rev = false) const {
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218};
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243public:
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258private:
260 const char *const *SubRegIndexNames;
261 const SubRegCoveredBits *SubRegIdxRanges;
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267 regclass_iterator RegClassBegin, RegClassEnd;
271 unsigned HwMode;
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273protected:
280 unsigned Mode = 0);
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282public:
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322 return true;
323 return false;
324 }
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330 if (VT == MVT::Untyped)
331 return true;
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334 return true;
335 }
336 return false;
337 }
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347 while (*I != MVT::Other)
348 ++I;
349 return I;
350 }
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356 MVT VT = MVT::Other) const;
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363 MVT VT = MVT::Other) const;
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396 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
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398 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
399 }
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403 return InfoDesc->InAllocatableClass[RegNo];
404 }
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410 "This is not a subregister index");
411 return SubRegIndexNames[SubIdx-1];
412 }
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417 unsigned getSubRegIdxSize(unsigned Idx) const;
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422 unsigned getSubRegIdxOffset(unsigned Idx) const;
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430 return SubRegIndexLaneMasks[SubIdx];
431 }
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469 if (RegA == RegB)
470 return true;
473 return false;
474 }
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495 lookThruSingleUseCopyChain(Register SrcReg,
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515 return nullptr;
516 }
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539 return nullptr;
540 }
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546 return nullptr;
547 }
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564 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
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587 virtual std::optionalstd::string
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638 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
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660 virtual bool
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698 unsigned SrcSubReg) const;
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705 unsigned DefSubReg,
707 unsigned SrcSubReg) const {
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709 return findCommonRegClass(DefRC, DefSubReg, SrcRC, SrcSubReg) != nullptr;
710 }
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726 assert(Idx == 0 && "Target has no sub-registers");
727 return RC;
728 }
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734 unsigned SubRegIdx) const {
735 return nullptr;
736 }
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752 if (!a) return b;
753 if (!b) return a;
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766 if (!a)
767 return b;
768 if (!b)
769 return a;
771 }
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778 if (!IdxA)
779 return Mask;
781 }
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792 if (!IdxA)
793 return LaneMask;
795 }
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798 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
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806 return nullptr;
807 }
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864 unsigned &PreA, unsigned &PreB) const;
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890 return RegClassBegin[i];
891 }
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930 return RC;
931 }
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949 unsigned PSetID) const {
950 return PSetID;
951 }
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972 unsigned Idx) const = 0;
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1000 virtual bool
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1036 return false;
1037 }
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1048 return false;
1049 }
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1055 return false;
1056 }
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1061 return false;
1062 }
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1071 int &FrameIdx) const {
1072 return false;
1073 }
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1081 virtual bool canRealignStack(const MachineFunction &MF) const;
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1085 virtual bool shouldRealignStack(const MachineFunction &MF) const;
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1095 int Idx) const {
1096 return 0;
1097 }
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1104 return false;
1105 }
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1110 int FrameIdx,
1111 int64_t Offset) const {
1112 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1113 "target");
1114 }
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1126 int64_t Offset) const {
1127 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1128 }
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1136 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
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1140 llvm_unreachable("getDwarfRegNumForVirtReg does not exist on this target");
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1152 return false;
1153 }
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1194 unsigned DstSubReg,
1197 { return true; }
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1202 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
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1214 virtual bool
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1225 return false;
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1292 const unsigned RCMaskWords;
1293 unsigned SubReg = 0;
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1297public:
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1302 bool IncludeSelf = false)
1303 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1304 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1305 if (!IncludeSelf)
1306 ++*this;
1307 }
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1322 assert(isValid() && "Cannot move iterator past end.");
1323 Mask += RCMaskWords;
1324 SubReg = *Idx++;
1325 if (!SubReg)
1326 Idx = nullptr;
1327 }
1328};
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1339 const unsigned NumRegClasses;
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1343 unsigned Base = 0;
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1346 unsigned Idx = 0;
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1348 unsigned ID = 0;
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1355 void moveToNextID() {
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1359 while (!CurrentChunk) {
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1361 Base += 32;
1362 if (Base >= NumRegClasses) {
1363 ID = NumRegClasses;
1364 return;
1365 }
1366 CurrentChunk = *++Mask;
1367 Idx = Base;
1368 }
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1388 void moveNBits(unsigned NumBits) {
1389 assert(NumBits < 32 && "Undefined behavior spotted!");
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1391 CurrentChunk >>= NumBits;
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1393 Idx += NumBits;
1394 }
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1396public:
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1402 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
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1404 moveToNextID();
1405 }
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1411 unsigned getID() const { return ID; }
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1416 moveToNextID();
1417 }
1418};
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1437 const TargetRegisterInfo *TRI = nullptr,
1438 unsigned SubIdx = 0,
1439 const MachineRegisterInfo *MRI = nullptr);
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1454 const TargetRegisterInfo *TRI);
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1459 const MachineRegisterInfo &RegInfo,
1460 const TargetRegisterInfo *TRI);
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1462}
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1464#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
A common definition of LaneBitmask for use in TableGen and CodeGen.
Register const TargetRegisterInfo * TRI
Promote Memory to Register
static StringRef getName(Value *V)
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
This file defines the SmallVector class.
static const TargetRegisterClass * getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg, TypeT Ty)
static const TargetRegisterClass * getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, MCRegister Reg2, TypeT Ty)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void operator++()
Advance iterator to the next entry.
Definition TargetRegisterInfo.h:1414
unsigned getID() const
Returns the current register class ID.
Definition TargetRegisterInfo.h:1411
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
Definition TargetRegisterInfo.h:1401
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition TargetRegisterInfo.h:1408
LiveInterval - This class represents the liveness of a register, or stack slot.
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
iota_range< MCRegUnit > regunits() const
Returns an iterator range over all regunits.
const char * getRegClassName(const MCRegisterClass *Class) const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
StringRef - Represent a constant reference to a string, i.e.
void operator++()
Advance iterator to the next entry.
Definition TargetRegisterInfo.h:1321
unsigned getSubReg() const
Returns the current sub-register index.
Definition TargetRegisterInfo.h:1313
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
Definition TargetRegisterInfo.h:1318
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
Definition TargetRegisterInfo.h:1300
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition TargetRegisterInfo.h:1310
const LaneBitmask LaneMask
Definition TargetRegisterInfo.h:54
unsigned getNumRegs() const
Return the number of registers in this class.
Definition TargetRegisterInfo.h:82
const uint8_t TSFlags
Configurable target specific flags.
Definition TargetRegisterInfo.h:63
ArrayRef< MCPhysReg > getRegisters() const
Definition TargetRegisterInfo.h:84
bool isBaseClass() const
Return true if this register class has a defined BaseClassOrder.
Definition TargetRegisterInfo.h:127
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
Definition TargetRegisterInfo.h:179
unsigned getID() const
Return the register class ID number.
Definition TargetRegisterInfo.h:74
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF, bool Rev=false) const
Returns the preferred order for allocating registers from this register class in MF.
Definition TargetRegisterInfo.h:207
const MCPhysReg * iterator
Definition TargetRegisterInfo.h:47
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition TargetRegisterInfo.h:65
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition TargetRegisterInfo.h:95
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition TargetRegisterInfo.h:124
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &, bool Rev)
Definition TargetRegisterInfo.h:71
iterator end() const
Definition TargetRegisterInfo.h:79
uint8_t getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition TargetRegisterInfo.h:114
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition TargetRegisterInfo.h:136
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition TargetRegisterInfo.h:131
const bool GlobalPriority
Definition TargetRegisterInfo.h:60
bool expensiveOrImpossibleToCopy() const
Definition TargetRegisterInfo.h:118
ArrayRef< unsigned > superclasses() const
Returns a list of super-classes.
Definition TargetRegisterInfo.h:186
const uint16_t * SuperRegIndices
Definition TargetRegisterInfo.h:53
const MCRegisterClass * MC
Definition TargetRegisterInfo.h:51
const MCPhysReg * const_iterator
Definition TargetRegisterInfo.h:48
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition TargetRegisterInfo.h:148
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
Definition TargetRegisterInfo.h:68
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition TargetRegisterInfo.h:215
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition TargetRegisterInfo.h:143
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
Definition TargetRegisterInfo.h:104
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition TargetRegisterInfo.h:192
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition TargetRegisterInfo.h:168
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
Definition TargetRegisterInfo.h:57
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition TargetRegisterInfo.h:89
iterator begin() const
begin/end - Return all of the registers in this class.
Definition TargetRegisterInfo.h:78
const uint16_t SuperClassesSize
Definition TargetRegisterInfo.h:70
const unsigned * SuperClasses
Definition TargetRegisterInfo.h:69
const uint32_t * SubClassMask
Definition TargetRegisterInfo.h:52
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition TargetRegisterInfo.h:607
virtual SmallVector< StringLiteral > getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const
Definition TargetRegisterInfo.h:1266
const TargetRegisterClass *const * regclass_iterator
Definition TargetRegisterInfo.h:244
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition TargetRegisterInfo.h:1125
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
Definition TargetRegisterInfo.h:345
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
Definition TargetRegisterInfo.h:327
bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const
Returns true if Reg contains RegUnit.
Definition TargetRegisterInfo.h:477
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
~TargetRegisterInfo() override
unsigned reverseComposeSubRegIndices(unsigned a, unsigned b) const
Return a subregister index that will compose to give you the subregister index.
Definition TargetRegisterInfo.h:765
iterator_range< regclass_iterator > regclasses() const
Definition TargetRegisterInfo.h:878
virtual const int * getRegUnitPressureSets(MCRegUnit RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual const TargetRegisterClass * getPhysRegBaseClass(MCRegister Reg) const
Return target defined base register class for a physical register.
Definition TargetRegisterInfo.h:805
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
Definition TargetRegisterInfo.h:594
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition TargetRegisterInfo.h:725
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition TargetRegisterInfo.h:888
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
Definition TargetRegisterInfo.h:1041
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
Definition TargetRegisterInfo.h:917
virtual bool isVirtualFrameRegister(MCRegister Reg) const
Some targets delay assigning the frame until late and use a placeholder to represent it earlier.
Definition TargetRegisterInfo.h:1259
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
Definition TargetRegisterInfo.h:1215
virtual bool eliminateFrameIndicesBackwards() const
Process frame indices in reverse block order.
Definition TargetRegisterInfo.h:1160
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition TargetRegisterInfo.h:751
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
Definition TargetRegisterInfo.h:822
virtual bool isIgnoredCVReg(MCRegister LLVMReg) const
Definition TargetRegisterInfo.h:1272
virtual bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const
Returns true if RC is a class/subclass of general purpose register.
Definition TargetRegisterInfo.h:661
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
Definition TargetRegisterInfo.h:1031
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual const MCPhysReg * getIPRACSRegs(const MachineFunction *MF) const
Return a null-terminated list of all of the callee-saved registers on this target when IPRA is on.
Definition TargetRegisterInfo.h:514
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition TargetRegisterInfo.h:545
virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const
Get the scale factor of spill weight for this register class.
const MVT::SimpleValueType * vt_iterator
Definition TargetRegisterInfo.h:245
virtual bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const
Returns true if the register is considered uniform.
Definition TargetRegisterInfo.h:615
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition TargetRegisterInfo.h:302
virtual std::optional< std::string > explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns either a string explaining why the given register is reserved for this function,...
Definition TargetRegisterInfo.h:588
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
Definition TargetRegisterInfo.h:1047
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition TargetRegisterInfo.h:408
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition TargetRegisterInfo.h:536
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Definition TargetRegisterInfo.h:826
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
Definition TargetRegisterInfo.h:464
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
Definition TargetRegisterInfo.h:1094
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
Definition TargetRegisterInfo.h:393
virtual bool isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a general purpose register.
Definition TargetRegisterInfo.h:654
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
Definition TargetRegisterInfo.h:790
regclass_iterator regclass_begin() const
Register class iterators.
Definition TargetRegisterInfo.h:876
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
Definition TargetRegisterInfo.h:948
unsigned getNumRegClasses() const
Definition TargetRegisterInfo.h:882
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
Definition TargetRegisterInfo.h:558
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
Definition TargetRegisterInfo.h:1026
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
Definition TargetRegisterInfo.h:1252
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition TargetRegisterInfo.h:341
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
Definition TargetRegisterInfo.h:939
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition TargetRegisterInfo.h:428
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
virtual int64_t getDwarfRegNumForVirtReg(Register RegNum, bool isEH) const
Definition TargetRegisterInfo.h:1139
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition TargetRegisterInfo.h:926
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
Definition TargetRegisterInfo.h:870
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition TargetRegisterInfo.h:550
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
Definition TargetRegisterInfo.h:1076
virtual bool isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg can be used as an argument to a function.
Definition TargetRegisterInfo.h:642
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition TargetRegisterInfo.h:314
virtual std::optional< uint8_t > getVRegFlagValue(StringRef Name) const
Definition TargetRegisterInfo.h:1261
virtual const TargetRegisterClass * getSubRegisterClass(const TargetRegisterClass *SuperRC, unsigned SubRegIdx) const
Return a register class that can be used for a subregister copy from/into SuperRC at SubRegIdx.
Definition TargetRegisterInfo.h:733
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
Definition TargetRegisterInfo.h:1053
virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual unsigned getRegUnitWeight(MCRegUnit RegUnit) const =0
Get the weight in units of pressure for this register unit.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
Definition TargetRegisterInfo.h:1035
regclass_iterator regclass_end() const
Definition TargetRegisterInfo.h:877
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
Definition TargetRegisterInfo.h:776
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition TargetRegisterInfo.h:1088
virtual bool shouldAnalyzePhysregInMachineLoopInfo(MCRegister R) const
Returns true if MachineLoopInfo should analyze the given physreg for loop invariance.
Definition TargetRegisterInfo.h:622
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition TargetRegisterInfo.h:1147
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition TargetRegisterInfo.h:704
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition TargetRegisterInfo.h:672
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
Definition TargetRegisterInfo.h:631
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
Definition TargetRegisterInfo.h:1070
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
Definition TargetRegisterInfo.h:1118
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition TargetRegisterInfo.h:610
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
Definition TargetRegisterInfo.h:1109
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition TargetRegisterInfo.h:468
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual unsigned getNumSupportedRegs(const MachineFunction &) const
Return the number of registers for the function. (may overestimate)
Definition TargetRegisterInfo.h:286
virtual ArrayRef< const char * > getRegMaskNames() const =0
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)
virtual bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg is a fixed register.
Definition TargetRegisterInfo.h:648
const TargetRegisterClass * findCommonRegClass(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Find a common register class that can accomodate both the source and destination operands of a copy-l...
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition TargetRegisterInfo.h:1244
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition TargetRegisterInfo.h:308
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
Definition TargetRegisterInfo.h:1176
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition TargetRegisterInfo.h:319
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
Definition TargetRegisterInfo.h:834
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition TargetRegisterInfo.h:1103
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
Definition TargetRegisterInfo.h:811
virtual const TargetRegisterClass * getPointerRegClass(unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition TargetRegisterInfo.h:908
virtual unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
Definition TargetRegisterInfo.h:816
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
Definition TargetRegisterInfo.h:668
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, MCRegister PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
Definition TargetRegisterInfo.h:600
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
Definition TargetRegisterInfo.h:1190
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition TargetRegisterInfo.h:894
virtual bool regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const
When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPr...
Definition TargetRegisterInfo.h:1224
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition TargetRegisterInfo.h:402
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
Definition TargetRegisterInfo.h:1012
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
Definition TargetRegisterInfo.h:1060
static constexpr TypeSize getFixed(ScalarTy ExactSize)
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
LLVM_ABI Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
ArrayRef(const T &OneElt) -> ArrayRef< T >
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_ABI Printable printVRegOrUnit(VirtRegOrUnit VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Definition TargetRegisterInfo.h:231
unsigned RegWeight
Definition TargetRegisterInfo.h:232
unsigned WeightLimit
Definition TargetRegisterInfo.h:233
Extra information, not in MCRegisterDesc, about registers.
Definition TargetRegisterInfo.h:222
const bool * InAllocatableClass
Definition TargetRegisterInfo.h:226
unsigned NumCosts
Definition TargetRegisterInfo.h:224
const uint8_t * CostPerUse
Definition TargetRegisterInfo.h:223
unsigned VTListOffset
Definition TargetRegisterInfo.h:248
unsigned SpillSize
Definition TargetRegisterInfo.h:247
unsigned RegSize
Definition TargetRegisterInfo.h:247
unsigned SpillAlignment
Definition TargetRegisterInfo.h:247
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...
Definition TargetRegisterInfo.h:253
uint16_t Offset
Definition TargetRegisterInfo.h:254
uint16_t Size
Definition TargetRegisterInfo.h:255
unsigned operator()(Register Reg) const
Definition TargetRegisterInfo.h:1423
Register argument_type
Definition TargetRegisterInfo.h:1422