X86DomainReassignment.cpp Source File (original) (raw)

28#include

30using namespace llvm;

32#define DEBUG_TYPE "x86-domain-reassignment"

34 STATISTIC(NumClosuresConverted, "Number of closures converted by the pass");

37 "disable-x86-domain-reassignment", cl::Hidden,

38 cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false));

40namespace {

41enum RegDomain { NoDomain = -1, GPRDomain, MaskDomain, OtherDomain, NumDomains };

45 return X86::VK16RegClass.hasSubClassEq(RC);

46}

50 if (TRI->isGeneralPurposeRegisterClass(RC))

51 return GPRDomain;

52 if (isMask(RC, TRI))

53 return MaskDomain;

54 return OtherDomain;

55}

61 if (X86::GR8RegClass.hasSubClassEq(SrcRC))

62 return &X86::VK8RegClass;

63 if (X86::GR16RegClass.hasSubClassEq(SrcRC))

64 return &X86::VK16RegClass;

65 if (X86::GR32RegClass.hasSubClassEq(SrcRC))

66 return &X86::VK32RegClass;

67 if (X86::GR64RegClass.hasSubClassEq(SrcRC))

68 return &X86::VK64RegClass;

70 return nullptr;

71}

74class InstrConverterBase {

75protected:

76 unsigned SrcOpcode;

78public:

79 InstrConverterBase(unsigned SrcOpcode) : SrcOpcode(SrcOpcode) {}

81 virtual ~InstrConverterBase() = default;

84 virtual bool isLegal(const MachineInstr *MI,

85 const TargetInstrInfo *TII) const {

86 assert(MI->getOpcode() == SrcOpcode &&

87 "Wrong instruction passed to converter");

88 return true;

89 }

94 virtual bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,

95 MachineRegisterInfo *MRI) const = 0;

98 virtual double getExtraCost(const MachineInstr *MI,

99 MachineRegisterInfo *MRI) const = 0;

100};

101

102

103

104

105class InstrIgnore : public InstrConverterBase {

106public:

107 InstrIgnore(unsigned SrcOpcode) : InstrConverterBase(SrcOpcode) {}

108

109 bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,

110 MachineRegisterInfo *MRI) const override {

111 assert(isLegal(MI, TII) && "Cannot convert instruction");

112 return false;

113 }

114

115 double getExtraCost(const MachineInstr *MI,

116 MachineRegisterInfo *MRI) const override {

117 return 0;

118 }

119};

120

121

122class InstrReplacer : public InstrConverterBase {

123public:

124

125 unsigned DstOpcode;

126

127 InstrReplacer(unsigned SrcOpcode, unsigned DstOpcode)

128 : InstrConverterBase(SrcOpcode), DstOpcode(DstOpcode) {}

129

130 bool isLegal(const MachineInstr *MI,

131 const TargetInstrInfo *TII) const override {

132 if (!InstrConverterBase::isLegal(MI, TII))

133 return false;

134

135

136 for (const auto &MO : MI->implicit_operands())

137 if (MO.isReg() && MO.isDef() && !MO.isDead() &&

138 TII ->get(DstOpcode).hasImplicitDefOfPhysReg(MO.getReg()))

139 return false;

140 return true;

141 }

142

143 bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,

144 MachineRegisterInfo *MRI) const override {

145 assert(isLegal(MI, TII) && "Cannot convert instruction");

146 MachineInstrBuilder Bld =

147 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(DstOpcode));

148

149

150 for (auto &Op : MI->explicit_operands())

152 return true;

153 }

154

155 double getExtraCost(const MachineInstr *MI,

156 MachineRegisterInfo *MRI) const override {

157

158 return 0;

159 }

160};

161

162

163

164class InstrReplacerDstCOPY : public InstrConverterBase {

165public:

166 unsigned DstOpcode;

167

168 InstrReplacerDstCOPY(unsigned SrcOpcode, unsigned DstOpcode)

169 : InstrConverterBase(SrcOpcode), DstOpcode(DstOpcode) {}

170

171 bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,

172 MachineRegisterInfo *MRI) const override {

173 assert(isLegal(MI, TII) && "Cannot convert instruction");

174 MachineBasicBlock *MBB = MI->getParent();

176

178 MRI->createVirtualRegister(TII->getRegClass(TII->get(DstOpcode), 0));

181 Bld.add(MO);

182

184 .add(MI->getOperand(0))

186

187 return true;

188 }

189

190 double getExtraCost(const MachineInstr *MI,

191 MachineRegisterInfo *MRI) const override {

192

193

194 return 0;

195 }

196};

197

198

199class InstrCOPYReplacer : public InstrReplacer {

200public:

201 RegDomain DstDomain;

202

203 InstrCOPYReplacer(unsigned SrcOpcode, RegDomain DstDomain, unsigned DstOpcode)

204 : InstrReplacer(SrcOpcode, DstOpcode), DstDomain(DstDomain) {}

205

206 bool isLegal(const MachineInstr *MI,

207 const TargetInstrInfo *TII) const override {

208 if (!InstrConverterBase::isLegal(MI, TII))

209 return false;

210

211

212

213 Register DstReg = MI->getOperand(0).getReg();

214 if (DstReg.isPhysical() && (X86::GR8RegClass.contains(DstReg) ||

215 X86::GR16RegClass.contains(DstReg)))

216 return false;

217 Register SrcReg = MI->getOperand(1).getReg();

218 if (SrcReg.isPhysical() && (X86::GR8RegClass.contains(SrcReg) ||

219 X86::GR16RegClass.contains(SrcReg)))

220 return false;

221

222 return true;

223 }

224

225 double getExtraCost(const MachineInstr *MI,

226 MachineRegisterInfo *MRI) const override {

227 assert(MI->getOpcode() == TargetOpcode::COPY && "Expected a COPY");

228

229 for (const auto &MO : MI->operands()) {

230

231

232

233 if (MO.getReg().isPhysical())

234 return 1;

235

236 RegDomain OpDomain = getDomain(MRI->getRegClass(MO.getReg()),

237 MRI->getTargetRegisterInfo());

238

239

240 if (OpDomain == DstDomain)

241 return -1;

242 }

243 return 0;

244 }

245};

246

247

248class InstrReplaceWithCopy : public InstrConverterBase {

249public:

250

251 unsigned SrcOpIdx;

252

253 InstrReplaceWithCopy(unsigned SrcOpcode, unsigned SrcOpIdx)

254 : InstrConverterBase(SrcOpcode), SrcOpIdx(SrcOpIdx) {}

255

256 bool convertInstr(MachineInstr *MI, const TargetInstrInfo *TII,

257 MachineRegisterInfo *MRI) const override {

258 assert(isLegal(MI, TII) && "Cannot convert instruction");

260 TII->get(TargetOpcode::COPY))

261 .add({MI->getOperand(0), MI->getOperand(SrcOpIdx)});

262 return true;

263 }

264

265 double getExtraCost(const MachineInstr *MI,

266 MachineRegisterInfo *MRI) const override {

267 return 0;

268 }

269};

270

271

272

273typedef std::pair<int, unsigned> InstrConverterBaseKeyTy;

274

276 InstrConverterBaseMap;

277

278

279

280

281

282

283

284

285

286

287

288

289class Closure {

290private:

291

292 DenseSet Edges;

293

294

295 SmallVector<MachineInstr *, 8> Instrs;

296

297

298 std::bitset LegalDstDomains;

299

300

301

302 unsigned ID;

303

304public:

305 Closure(unsigned ID, std::initializer_list LegalDstDomainList) : ID(ID) {

306 for (RegDomain D : LegalDstDomainList)

307 LegalDstDomains.set(D);

308 }

309

310

311 void setAllIllegal() { LegalDstDomains.reset(); }

312

313

314 bool hasLegalDstDomain() const { return LegalDstDomains.any(); }

315

316

317 bool isLegal(RegDomain RD) const { return LegalDstDomains[RD]; }

318

319

320 void setIllegal(RegDomain RD) { LegalDstDomains[RD] = false; }

321

322 bool empty() const { return Edges.empty(); }

323

324 bool insertEdge(Register Reg) { return Edges.insert(Reg).second; }

325

326 using const_edge_iterator = DenseSet::const_iterator;

328

329 void addInstruction(MachineInstr *I) {

330 Instrs.push_back(I);

331 }

332

334 return Instrs;

335 }

336

338 dbgs() << "Registers: ";

339 bool First = true;

342 dbgs() << ", ";

345 }

346 dbgs() << "\n" << "Instructions:";

347 for (MachineInstr *MI : Instrs) {

348 dbgs() << "\n ";

350 }

351 dbgs() << "\n";

352 }

353

354 unsigned getID() const {

355 return ID;

356 }

357

358};

359

361 const X86Subtarget *STI = nullptr;

362 MachineRegisterInfo *MRI = nullptr;

363 const X86InstrInfo *TII = nullptr;

364

365

366 DenseMap<Register, unsigned> EnclosedEdges;

367

368

369 DenseMap<MachineInstr *, unsigned> EnclosedInstrs;

370

371public:

372 static char ID;

373

374 X86DomainReassignment() : MachineFunctionPass(ID) { }

375

376 bool runOnMachineFunction(MachineFunction &MF) override;

377

378 void getAnalysisUsage(AnalysisUsage &AU) const override {

381 }

382

383 StringRef getPassName() const override {

384 return "X86 Domain Reassignment Pass";

385 }

386

387private:

388

389 InstrConverterBaseMap Converters;

390

391

392 void initConverters();

393

394

395 void buildClosure(Closure &, Register Reg);

396

397

398

400 SmallVectorImpl &Worklist);

401

402

403 void reassign(const Closure &C, RegDomain Domain) const;

404

405

406

407 bool encloseInstr(Closure &C, MachineInstr *MI);

408

409

410 bool isReassignmentProfitable(const Closure &C, RegDomain Domain) const;

411

412

413 double calculateCost(const Closure &C, RegDomain Domain) const;

414};

415

416char X86DomainReassignment::ID = 0;

417

418}

419

420bool X86DomainReassignment::visitRegister(Closure &C, Register Reg,

424 return true;

425

426 auto I = EnclosedEdges.find(Reg);

427 if (I != EnclosedEdges.end()) {

428 if (I->second != C.getID()) {

429 C.setAllIllegal();

430 return false;

431 }

432 return true;

433 }

434

435 if ( MRI ->hasOneDef(Reg))

436 return true;

437

438 RegDomain RD = getDomain(MRI->getRegClass(Reg), MRI->getTargetRegisterInfo());

439

440 if (Domain == NoDomain)

442

444 return true;

445

447 return true;

448}

449

450bool X86DomainReassignment::encloseInstr(Closure &C, MachineInstr *MI) {

452 if (!Inserted) {

453 if (I->second != C.getID()) {

454

455

456 C.setAllIllegal();

457 return false;

458 }

459 return true;

460 }

461

462 C.addInstruction(MI);

463

464

465

466

467 for (int i = 0; i != NumDomains; ++i) {

468 if (C.isLegal((RegDomain)i)) {

469 auto I = Converters.find({i, MI->getOpcode()});

470 if (I == Converters.end() || ->second->isLegal(MI, TII))

471 C.setIllegal((RegDomain)i);

472 }

473 }

474 return C.hasLegalDstDomain();

475}

476

477double X86DomainReassignment::calculateCost(const Closure &C,

478 RegDomain DstDomain) const {

479 assert(C.isLegal(DstDomain) && "Cannot calculate cost for illegal closure");

480

481 double Cost = 0.0;

482 for (auto *MI : C.instructions())

483 Cost += Converters.find({DstDomain, MI->getOpcode()})

484 ->second->getExtraCost(MI, MRI);

486}

487

488bool X86DomainReassignment::isReassignmentProfitable(const Closure &C,

489 RegDomain Domain) const {

490 return calculateCost(C, Domain) < 0.0;

491}

492

493void X86DomainReassignment::reassign(const Closure &C, RegDomain Domain) const {

494 assert(C.isLegal(Domain) && "Cannot convert illegal closure");

495

496

497

498 SmallVector<MachineInstr *, 8> ToErase;

499 for (auto *MI : C.instructions())

500 if (Converters.find({Domain, MI->getOpcode()})

501 ->second->convertInstr(MI, TII, MRI))

503

504

505

508 for (auto &MO : MRI->use_operands(Reg)) {

509 if (MO.isReg())

510

511

512 MO.setSubReg(0);

513 }

514 }

515

516 for (auto *MI : ToErase)

517 MI->eraseFromParent();

518}

519

520

521

524 if (.mayLoadOrStore())

525 return false;

526

529 if (MemOpStart == -1)

530 return false;

531

533 for (unsigned MemOpIdx = MemOpStart,

535 MemOpIdx < MemOpEnd; ++MemOpIdx) {

537 if (Op.isReg() && Op.getReg() == Reg)

538 return true;

539 }

540 return false;

541}

542

543void X86DomainReassignment::buildClosure(Closure &C, Register Reg) {

545 RegDomain Domain = NoDomain;

546 visitRegister(C, Reg, Domain, Worklist);

547 while (!Worklist.empty()) {

549

550

551 if (.insertEdge(CurReg))

552 continue;

553 EnclosedEdges[Reg] = C.getID();

554

555 MachineInstr *DefMI = MRI->getVRegDef(CurReg);

556 if (!encloseInstr(C, DefMI))

557 return;

558

559

560

561

565 if (MemOp != -1)

568 if (OpIdx == MemOp) {

569

571 continue;

572 }

574 if (.isReg() || .isUse())

575 continue;

576 if (!visitRegister(C, Op.getReg(), Domain, Worklist))

577 return;

578 }

579

580

581 for (auto &UseMI : MRI->use_nodbg_instructions(CurReg)) {

582

583

585 C.setAllIllegal();

586 return;

587 }

588 if (!encloseInstr(C, &UseMI))

589 return;

590

591 for (auto &DefOp : UseMI.defs()) {

592 if (!DefOp.isReg())

593 continue;

594

595 Register DefReg = DefOp.getReg();

597 C.setAllIllegal();

598 return;

599 }

600 if (!visitRegister(C, DefReg, Domain, Worklist))

601 return;

602 }

603 }

604 }

605}

606

607void X86DomainReassignment::initConverters() {

608 Converters[{MaskDomain, TargetOpcode::PHI}] =

609 std::make_unique(TargetOpcode::PHI);

610

611 Converters[{MaskDomain, TargetOpcode::IMPLICIT_DEF}] =

612 std::make_unique(TargetOpcode::IMPLICIT_DEF);

613

614 Converters[{MaskDomain, TargetOpcode::INSERT_SUBREG}] =

615 std::make_unique(TargetOpcode::INSERT_SUBREG, 2);

616

617 Converters[{MaskDomain, TargetOpcode::COPY}] =

618 std::make_unique(TargetOpcode::COPY, MaskDomain,

619 TargetOpcode::COPY);

620

621 auto createReplacerDstCOPY = [&](unsigned From, unsigned To) {

622 Converters[{MaskDomain, From}] =

623 std::make_unique(From, To);

624 };

625

626#define GET_EGPR_IF_ENABLED(OPC) STI->hasEGPR() ? OPC##_EVEX : OPC

627 createReplacerDstCOPY(X86::MOVZX32rm16, GET_EGPR_IF_ENABLED(X86::KMOVWkm));

628 createReplacerDstCOPY(X86::MOVZX64rm16, GET_EGPR_IF_ENABLED(X86::KMOVWkm));

629

630 createReplacerDstCOPY(X86::MOVZX32rr16, GET_EGPR_IF_ENABLED(X86::KMOVWkk));

631 createReplacerDstCOPY(X86::MOVZX64rr16, GET_EGPR_IF_ENABLED(X86::KMOVWkk));

632

633 if (STI->hasDQI()) {

634 createReplacerDstCOPY(X86::MOVZX16rm8, GET_EGPR_IF_ENABLED(X86::KMOVBkm));

635 createReplacerDstCOPY(X86::MOVZX32rm8, GET_EGPR_IF_ENABLED(X86::KMOVBkm));

636 createReplacerDstCOPY(X86::MOVZX64rm8, GET_EGPR_IF_ENABLED(X86::KMOVBkm));

637

638 createReplacerDstCOPY(X86::MOVZX16rr8, GET_EGPR_IF_ENABLED(X86::KMOVBkk));

639 createReplacerDstCOPY(X86::MOVZX32rr8, GET_EGPR_IF_ENABLED(X86::KMOVBkk));

640 createReplacerDstCOPY(X86::MOVZX64rr8, GET_EGPR_IF_ENABLED(X86::KMOVBkk));

641 }

642

643 auto createReplacer = [&](unsigned From, unsigned To) {

644 Converters[{MaskDomain, From}] = std::make_unique(From, To);

645 };

646

650 createReplacer(X86::SHR16ri, X86::KSHIFTRWki);

651 createReplacer(X86::SHL16ri, X86::KSHIFTLWki);

652 createReplacer(X86::NOT16r, X86::KNOTWkk);

653 createReplacer(X86::OR16rr, X86::KORWkk);

654 createReplacer(X86::AND16rr, X86::KANDWkk);

655 createReplacer(X86::XOR16rr, X86::KXORWkk);

656

657 bool HasNDD = STI->hasNDD();

658 if (HasNDD) {

659 createReplacer(X86::SHR16ri_ND, X86::KSHIFTRWki);

660 createReplacer(X86::SHL16ri_ND, X86::KSHIFTLWki);

661 createReplacer(X86::NOT16r_ND, X86::KNOTWkk);

662 createReplacer(X86::OR16rr_ND, X86::KORWkk);

663 createReplacer(X86::AND16rr_ND, X86::KANDWkk);

664 createReplacer(X86::XOR16rr_ND, X86::KXORWkk);

665 }

666

667 if (STI->hasBWI()) {

670

673

676

677 createReplacer(X86::SHR32ri, X86::KSHIFTRDki);

678 createReplacer(X86::SHR64ri, X86::KSHIFTRQki);

679

680 createReplacer(X86::SHL32ri, X86::KSHIFTLDki);

681 createReplacer(X86::SHL64ri, X86::KSHIFTLQki);

682

683 createReplacer(X86::ADD32rr, X86::KADDDkk);

684 createReplacer(X86::ADD64rr, X86::KADDQkk);

685

686 createReplacer(X86::NOT32r, X86::KNOTDkk);

687 createReplacer(X86::NOT64r, X86::KNOTQkk);

688

689 createReplacer(X86::OR32rr, X86::KORDkk);

690 createReplacer(X86::OR64rr, X86::KORQkk);

691

692 createReplacer(X86::AND32rr, X86::KANDDkk);

693 createReplacer(X86::AND64rr, X86::KANDQkk);

694

695 createReplacer(X86::ANDN32rr, X86::KANDNDkk);

696 createReplacer(X86::ANDN64rr, X86::KANDNQkk);

697

698 createReplacer(X86::XOR32rr, X86::KXORDkk);

699 createReplacer(X86::XOR64rr, X86::KXORQkk);

700

701 if (HasNDD) {

702 createReplacer(X86::SHR32ri_ND, X86::KSHIFTRDki);

703 createReplacer(X86::SHL32ri_ND, X86::KSHIFTLDki);

704 createReplacer(X86::ADD32rr_ND, X86::KADDDkk);

705 createReplacer(X86::NOT32r_ND, X86::KNOTDkk);

706 createReplacer(X86::OR32rr_ND, X86::KORDkk);

707 createReplacer(X86::AND32rr_ND, X86::KANDDkk);

708 createReplacer(X86::XOR32rr_ND, X86::KXORDkk);

709 createReplacer(X86::SHR64ri_ND, X86::KSHIFTRQki);

710 createReplacer(X86::SHL64ri_ND, X86::KSHIFTLQki);

711 createReplacer(X86::ADD64rr_ND, X86::KADDQkk);

712 createReplacer(X86::NOT64r_ND, X86::KNOTQkk);

713 createReplacer(X86::OR64rr_ND, X86::KORQkk);

714 createReplacer(X86::AND64rr_ND, X86::KANDQkk);

715 createReplacer(X86::XOR64rr_ND, X86::KXORQkk);

716 }

717

718

719

720

721

722 }

723

724 if (STI->hasDQI()) {

725 createReplacer(X86::ADD8rr, X86::KADDBkk);

726 createReplacer(X86::ADD16rr, X86::KADDWkk);

727

728 createReplacer(X86::AND8rr, X86::KANDBkk);

729

733

734 createReplacer(X86::NOT8r, X86::KNOTBkk);

735

736 createReplacer(X86::OR8rr, X86::KORBkk);

737

738 createReplacer(X86::SHR8ri, X86::KSHIFTRBki);

739 createReplacer(X86::SHL8ri, X86::KSHIFTLBki);

740

741

742

743

744

745

746 createReplacer(X86::XOR8rr, X86::KXORBkk);

747

748 if (HasNDD) {

749 createReplacer(X86::ADD8rr_ND, X86::KADDBkk);

750 createReplacer(X86::ADD16rr_ND, X86::KADDWkk);

751 createReplacer(X86::AND8rr_ND, X86::KANDBkk);

752 createReplacer(X86::NOT8r_ND, X86::KNOTBkk);

753 createReplacer(X86::OR8rr_ND, X86::KORBkk);

754 createReplacer(X86::SHR8ri_ND, X86::KSHIFTRBki);

755 createReplacer(X86::SHL8ri_ND, X86::KSHIFTLBki);

756 createReplacer(X86::XOR8rr_ND, X86::KXORBkk);

757 }

758 }

759#undef GET_EGPR_IF_ENABLED

760}

761

762bool X86DomainReassignment::runOnMachineFunction(MachineFunction &MF) {

764 return false;

766 return false;

767

769 dbgs() << "***** Machine Function before Domain Reassignment *****\n");

771

773

774

775

776

777

778 if (!STI->hasAVX512() || !STI->hasBWI())

779 return false;

780

782 assert(MRI->isSSA() && "Expected MIR to be in SSA form");

783

785 initConverters();

787

788 EnclosedEdges.clear();

789 EnclosedInstrs.clear();

790

791 std::vector Closures;

792

793

794 unsigned ClosureID = 0;

795 for (unsigned Idx = 0; Idx < MRI->getNumVirtRegs(); ++Idx) {

796 Register Reg = Register::index2VirtReg(Idx);

797

798

799 if (MRI->reg_nodbg_empty(Reg))

800 continue;

801

802

803 if ( MRI ->getTargetRegisterInfo()->isGeneralPurposeRegisterClass(

804 MRI->getRegClass(Reg)))

805 continue;

806

807

808 if (EnclosedEdges.contains(Reg))

809 continue;

810

811

812 Closure C(ClosureID++, {MaskDomain});

813 buildClosure(C, Reg);

814

815

816 if (.empty() && C.isLegal(MaskDomain))

817 Closures.push_back(std::move(C));

818 }

819

820 for (Closure &C : Closures) {

822 if (isReassignmentProfitable(C, MaskDomain)) {

823 reassign(C, MaskDomain);

824 ++NumClosuresConverted;

826 }

827 }

828

830 dbgs() << "***** Machine Function after Domain Reassignment *****\n");

832

834}

835

837 "X86 Domain Reassignment Pass", false, false)

838

839

841 return new X86DomainReassignment();

842}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Expand Atomic instructions

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

This file defines the DenseMap class.

const HexagonInstrInfo * TII

Promote Memory to Register

MachineInstr unsigned OpIdx

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

This file defines the SmallVector class.

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

#define GET_EGPR_IF_ENABLED(OPC)

static cl::opt< bool > DisableX86DomainReassignment("disable-x86-domain-reassignment", cl::Hidden, cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false))

static bool usedAsAddr(const MachineInstr &MI, Register Reg, const TargetInstrInfo *TII)

Definition X86DomainReassignment.cpp:522

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

std::pair< iterator, bool > try_emplace(KeyT &&Key, Ts &&...Args)

FunctionPass class - This class is used to implement most global optimizations.

Describe properties that are true of each instruction in the target description file.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

void print(raw_ostream &OS, const SlotIndexes *=nullptr) const

print - Print out the MachineFunction in a format suitable for debugging to the specified stream.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

unsigned getNumOperands() const

Retuns the total number of operands.

const MCInstrDesc & getDesc() const

Returns the target instruction descriptor of this MachineInstr.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

virtual void print(raw_ostream &OS, const Module *M) const

print - Print out the internal state of the pass.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

const X86InstrInfo * getInstrInfo() const override

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

int getMemoryOperandNo(uint64_t TSFlags)

unsigned getOperandBias(const MCInstrDesc &Desc)

Compute whether all of the def operands are repeated in the uses and therefore should be skipped.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

auto drop_begin(T &&RangeOrContainer, size_t N=1)

Return a range covering RangeOrContainer with the first N elements excluded.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

FunctionPass * createX86DomainReassignmentPass()

Return a Machine IR pass that reassigns instruction chains from one domain to another,...

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

iterator_range(Container &&) -> iterator_range< llvm::detail::IterOfRange< Container > >

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.