XtensaMCTargetDesc.cpp Source File (original) (raw)

24#define GET_INSTRINFO_MC_DESC

25#include "XtensaGenInstrInfo.inc"

27#define GET_REGINFO_MC_DESC

28#include "XtensaGenRegisterInfo.inc"

30#define GET_SUBTARGETINFO_MC_DESC

31#include "XtensaGenSubtargetInfo.inc"

33using namespace llvm;

36 bool Valid = false;

38 switch (Scale) {

39 case 1:

40 Valid = (OffsetVal >= 0 && OffsetVal <= 255);

41 break;

42 case 2:

43 Valid = (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0);

44 break;

45 case 4:

46 Valid = (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0);

47 break;

48 default:

49 break;

50 }

51 return Valid;

52}

55 int Scale = 0;

57 switch (Opcode) {

58 case Xtensa::L8UI:

59 case Xtensa::S8I:

60 Scale = 1;

61 break;

62 case Xtensa::L16SI:

63 case Xtensa::L16UI:

64 case Xtensa::S16I:

65 Scale = 2;

66 break;

67 case Xtensa::LEA_ADD:

69 default:

71 Scale = 4;

72 break;

73 }

75}

80 switch (RegNo) {

81 case Xtensa::BREG:

82 return FeatureBits[Xtensa::FeatureBoolean];

83 case Xtensa::CCOUNT:

84 case Xtensa::CCOMPARE0:

85 if (FeatureBits[Xtensa::FeatureTimers1])

86 return true;

87 [[fallthrough]];

88 case Xtensa::CCOMPARE1:

89 if (FeatureBits[Xtensa::FeatureTimers2])

90 return true;

91 [[fallthrough]];

92 case Xtensa::CCOMPARE2:

93 if (FeatureBits[Xtensa::FeatureTimers3])

94 return true;

95 return false;

96 case Xtensa::CONFIGID0:

98 case Xtensa::CONFIGID1:

100 case Xtensa::CPENABLE:

101 return FeatureBits[Xtensa::FeatureCoprocessor];

102 case Xtensa::DEBUGCAUSE:

104 case Xtensa::DEPC:

105 case Xtensa::EPC1:

106 case Xtensa::EXCCAUSE:

107 case Xtensa::EXCSAVE1:

108 case Xtensa::EXCVADDR:

109 return FeatureBits[Xtensa::FeatureException];

110 [[fallthrough]];

111 case Xtensa::EPC2:

112 case Xtensa::EPS2:

113 case Xtensa::EXCSAVE2:

114 if (FeatureBits[Xtensa::FeatureHighPriInterrupts])

115 return true;

116 [[fallthrough]];

117 case Xtensa::EPC3:

118 case Xtensa::EPS3:

119 case Xtensa::EXCSAVE3:

120 if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel3])

121 return true;

122 [[fallthrough]];

123 case Xtensa::EPC4:

124 case Xtensa::EPS4:

125 case Xtensa::EXCSAVE4:

126 if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel4])

127 return true;

128 [[fallthrough]];

129 case Xtensa::EPC5:

130 case Xtensa::EPS5:

131 case Xtensa::EXCSAVE5:

132 if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel5])

133 return true;

134 [[fallthrough]];

135 case Xtensa::EPC6:

136 case Xtensa::EPS6:

137 case Xtensa::EXCSAVE6:

138 if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel6])

139 return true;

140 [[fallthrough]];

141 case Xtensa::EPC7:

142 case Xtensa::EPS7:

143 case Xtensa::EXCSAVE7:

144 if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel7])

145 return true;

146 return false;

147 case Xtensa::INTENABLE:

148 return FeatureBits[Xtensa::FeatureInterrupt];

149 case Xtensa::INTERRUPT:

151 FeatureBits[Xtensa::FeatureInterrupt];

152 case Xtensa::INTSET:

153 case Xtensa::INTCLEAR:

155 FeatureBits[Xtensa::FeatureInterrupt];

156 case Xtensa::ICOUNT:

157 case Xtensa::ICOUNTLEVEL:

158 case Xtensa::IBREAKENABLE:

159 case Xtensa::DDR:

160 case Xtensa::IBREAKA0:

161 case Xtensa::IBREAKA1:

162 case Xtensa::DBREAKA0:

163 case Xtensa::DBREAKA1:

164 case Xtensa::DBREAKC0:

165 case Xtensa::DBREAKC1:

166 return FeatureBits[Xtensa::FeatureDebug];

167 case Xtensa::LBEG:

168 case Xtensa::LEND:

169 case Xtensa::LCOUNT:

170 return FeatureBits[Xtensa::FeatureLoop];

171 case Xtensa::LITBASE:

172 return FeatureBits[Xtensa::FeatureExtendedL32R];

173 case Xtensa::MEMCTL:

174 return FeatureBits[Xtensa::FeatureDataCache];

175 case Xtensa::ACCLO:

176 case Xtensa::ACCHI:

177 case Xtensa::M0:

178 case Xtensa::M1:

179 case Xtensa::M2:

180 case Xtensa::M3:

181 return FeatureBits[Xtensa::FeatureMAC16];

182 case Xtensa::MISC0:

183 case Xtensa::MISC1:

184 case Xtensa::MISC2:

185 case Xtensa::MISC3:

186 return FeatureBits[Xtensa::FeatureMiscSR];

187 case Xtensa::PRID:

189 case Xtensa::THREADPTR:

190 return FeatureBits[FeatureTHREADPTR];

191 case Xtensa::VECBASE:

192 return FeatureBits[Xtensa::FeatureRelocatableVector];

193 case Xtensa::FCR:

194 case Xtensa::FSR:

195 return FeatureBits[FeatureSingleFloat];

196 case Xtensa::F64R_LO:

197 case Xtensa::F64R_HI:

198 case Xtensa::F64S:

199 return FeatureBits[FeatureDFPAccel];

200 case Xtensa::WINDOWBASE:

201 case Xtensa::WINDOWSTART:

202 return FeatureBits[Xtensa::FeatureWindowed];

203 case Xtensa::ATOMCTL:

204 case Xtensa::SCOMPARE1:

205 return FeatureBits[Xtensa::FeatureS32C1I];

206 case Xtensa::NoRegister:

207 return false;

208 }

209

210 return true;

211}

212

213

215 MCRegister UserReg = Xtensa::NoRegister;

216

217 if (MRI.getEncodingValue(Xtensa::FCR) == Code) {

218 UserReg = Xtensa::FCR;

219 } else if (MRI.getEncodingValue(Xtensa::FSR) == Code) {

220 UserReg = Xtensa::FSR;

221 } else if (MRI.getEncodingValue(Xtensa::F64R_LO) == Code) {

222 UserReg = Xtensa::F64R_LO;

223 } else if (MRI.getEncodingValue(Xtensa::F64R_HI) == Code) {

224 UserReg = Xtensa::F64R_HI;

225 } else if (MRI.getEncodingValue(Xtensa::F64S) == Code) {

226 UserReg = Xtensa::F64S;

227 } else if (MRI.getEncodingValue(Xtensa::THREADPTR) == Code) {

228 UserReg = Xtensa::THREADPTR;

229 }

230

231 return UserReg;

232}

233

240

243 InitXtensaMCInstrInfo(X);

244 return X;

245}

246

248 unsigned SyntaxVariant,

253}

254

257 InitXtensaMCRegisterInfo(X, Xtensa::SP);

258 return X;

259}

260

263 return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS);

264}

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313}

unsigned const MachineRegisterInfo * MRI

#define LLVM_EXTERNAL_VISIBILITY

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

static MCTargetStreamer * createXtensaObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)

Definition XtensaMCTargetDesc.cpp:273

static MCInstrInfo * createXtensaMCInstrInfo()

Definition XtensaMCTargetDesc.cpp:241

static MCInstPrinter * createXtensaMCInstPrinter(const Triple &TT, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

Definition XtensaMCTargetDesc.cpp:247

static MCAsmInfo * createXtensaMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)

Definition XtensaMCTargetDesc.cpp:234

static MCTargetStreamer * createXtensaAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)

Definition XtensaMCTargetDesc.cpp:267

static MCRegisterInfo * createXtensaMCRegisterInfo(const Triple &TT)

Definition XtensaMCTargetDesc.cpp:255

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC()

Definition XtensaMCTargetDesc.cpp:277

static MCSubtargetInfo * createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

Definition XtensaMCTargetDesc.cpp:262

Container class for subtarget features.

This class is intended to be used as a base class for asm properties and features specific to the tar...

This is an instance of a target assembly language printer that converts an MCInst to valid target ass...

Interface to description of machine instruction set.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

Streaming machine code generation interface.

Generic base class for all target subtargets.

Target specific streamer interface.

StringRef - Represent a constant reference to a string, i.e.

Triple - Helper class for working with autoconf configuration names.

formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...

bool checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits, RegisterAccessType RA)

Definition XtensaMCTargetDesc.cpp:78

bool isValidAddrOffset(int Scale, int64_t OffsetVal)

Definition XtensaMCTargetDesc.cpp:35

MCRegister getUserRegister(unsigned Code, const MCRegisterInfo &MRI)

Definition XtensaMCTargetDesc.cpp:214

bool isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset)

Definition XtensaMCTargetDesc.cpp:54

This is an optimization pass for GlobalISel generic memory operations.

Target & getTheXtensaTarget()

MCAsmBackend * createXtensaAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

MCCodeEmitter * createXtensaMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)

RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.

static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)

RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.

static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)

RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.

static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)

RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.

static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)

RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.

static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)

static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)

RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.

static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)

RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.

static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)