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%! Detailed register description file for PCICFG.EXE by Ralf Brown %! %! Filename 80867180.PCI = Vendor 8086h, Device 7180h (Intel 440LX PCI-Host) %! Last Edit 15jan99 "Vernon C. Brooks" vbrooks@bellatlantic.net %! %! Reference: Intel document 29056402.PDF %! "82443LX PCI AGP CONTROLLER (PAC)" !begin 82443LX Registers in detail: [by Vernon C. Brooks and RB] Programmable Attribute Map \tC000-C3FF: %[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:1]{-W}%[5E:0]{-R}% \tF000-FFFF: %[59:5]{-W}%[59:4]{-R} \tC400-C7FF: %[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:5]{-W}%[5E:4]{-R} \tC800-CBFF: %[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:1]{-W}%[5F:0]{-R} \tCC00-CFFF: %[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:5]{-W}%[5F:4]{-R}% \t8000-9FFF: %[59:1]{-W}%[59:0]{-R} DRAM Row Types: %[55:1-0](DRT) %[55:3-2](DRT) %[55:5-4](DRT) %[55:7-6](DRT) %[55:9-8](DRT) %[55:11-10](DRT) %[55:13-12](DRT) %[55:15-14](DRT) DRAM Row Boundaries: %[60*8]4dM %[61*8]4dM %[62*8]4dM %[63*8]4dM %[64*8]4dM %[65*8]4dM %[66*8]4dM %[67*8]4dM DRAM Control: EDO auto-detect mode: %[57:5]ed SDRAM power management support: %[57:4]ed DRAM refresh rate: %[57:2-0](DRR) DRAM Timing: SDRAM RAS to CAS delay: %[58:7]|3 clocks;2 clocks| SDRAM CAS latency: %[58:6]|3 clocks;2 clocks| SDRAM RAS precharge time: %[58:5]|3 clocks;2 clocks| EDO DRAM read burst timing: %[58:4]|x333;x222| EDO DRAM write burst timing: %[58:3]|x333;x222| EDO RAS precharge time: %[58:2]|4 clocks;3 clocks| EDO RAS to CAS delay: %[58:1]|3 clocks;2 clocks| MA wait state: %[58:0]|slow;fast| Fixed DRAM Hole: %[68:7-6]|none;512K-640K;15M-16M;reserved| WSC# handshake: %[50:15]Ed \tHost frequency: %[50:14]|66 Mhz;60 Mhz| AGP-to-PCI access: %[50:11]ed \tPCI-agent access to aperture: %[50:10]Ed Graphics Aperture: %[50:9]ed \tDRAM integrity mode: %[50:8-7](integ) ECC diagnostics mode: %[50:6]ed \tMDA on PCI/ISA: %[50:5]|absent;present| CPU-to-PCI IDE posting: %[53:6]ed \tUSWC Write posting: %[53:5]ed SMRAM Control: SMM Space %[72:6]/Open/ %[72:5]/Closed/ %[72:4]/Locked/ %[72:3]/Enabled/ at %[72:2-0<12+32768]4x Error Command: enable SERR# on: %[90:7]/AGP outs. aperture/ %[90:6]/inv AGP DRAM access/ %[90:5]/invalid GATT/ %[90:4]/Target Abort/ %[90:3]/PCI Parity Error/ %[90:1]/multi-bit error/ %[90:0]/single-bit error/ Error Status: detected %[91:10]/AGP outside aperture/ %[91:9]/inv AGP DRAM access/ %[91:8]/invalid GATT/ %[91:4]/multi-bit error/ (row %[91:7-5]d), %[91:0]/single-bit error/ (row %[91:3-1]d) AGP Control: AGP %[A8:8]ed, sideband addr %[A8:9]ed, %[A8:1-0](AGPxfer) xfer rate forced ordering of snoop-writes/AGP reads is %[B0:15]Ed Graphics Aperture write/AGP read sync is %[B0:13]ed Graphics Translation Lookaside Buffer is %[B0:7]ed Aperture Size Mask (bits 27-22) = %[B4:5-0]6b Graphics Aperture Translation Table at %[B8:31-12<12]8x !end !enum DRT EDO reserved SDRAM empty !end !enum DRR disabled normal reserved reserved reserved reserved reserved !end !enum integ non-ECC EC-only reserved ECC !end !enum AGPxfer default 1x 2x illegal !end /vbrooks@bellatlantic.net