Native Floating Point - MATLAB & Simulink (original) (raw)

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HDL Coder native floating-point, the various features supported, how to model your design, generate HDL code, and verify the generated code

HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. These are some of the key features:

• Generation of target-independent HDL code that you can deploy on any FPGA or ASIC.
• Support for the full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes.
• Extensive support for math and trigonometric blocks.

Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.

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Topics

• Getting Started with HDL Coder Native Floating-Point Support
  Learn about the native floating point support in HDL Coder.
• Generate Target-Independent HDL Code with Native Floating-Point
  Generate HDL code from floating-point Simulink® models.
• Verify the Generated Code from Native Floating-Point
  How you can verify the generated code from the floating-point model using HDL Testbench, Cosimulation, and FPGA-in-the-loop.
• Numeric Considerations for Native Floating-Point
  Learn about nearest even-digit rounding, denormal numbers, exception handling, and relative accuracy and ULP considerations.
• ULP Considerations of Native Floating-Point Operators
  ULP considerations, ULP values of native floating-point operators, and adherence to IEEE-754 compliance.
• Latency Considerations with Native Floating Point
  Learn how to view the latency of a floating point operator and the various ways to customize it.
• Native Floating Point Support for Simulink Blocks
  List of operators and supported blocks in the floating-point model.
• Latency Values of Floating-Point Operators
  Latency values of operations supported in native floating-point mode.
• Critical Path Estimation Without Running Synthesis
  Find the estimated critical paths in your design without using third-party synthesis tools.
• HDL Block Properties: Native Floating Point
  HDL code generation parameters for native floating-point block implementations.
• Synthesis Benchmark of Common Native Floating Point Operators
  This example shows how to access and generate synthesis benchmarks for common native floating-point operators with Xilinx® Vivado® and Intel® Quartus® tool.

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