coder.HdlConfig - HDL codegen configuration object - MATLAB (original) (raw)

HDL codegen configuration object

Description

A coder.HdlConfig object contains the configuration parameters that the HDL codegen function requires to generate HDL code. To pass this object to the codegen function, use the -config option.

Creation

Syntax

collapse all

Create a coder.HdlConfig object hdlcfg.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config

Set the test bench name. In this example, the test bench function name ismlhdlc_dti_tb.

hdlcfg.TestBenchName = "mlhdlc_dti_tb";

Set the target language to Verilog®.

hdlcfg.TargetLanguage = "Verilog";

Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti.

codegen -config hdlcfg mlhdlc_dti

Create a coder.HdlConfig object hdlcfg.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config

Set the test bench name. In this example, the test bench function name ismlhdlc_dti_tb.

hdlcfg.TestBenchName = "mlhdlc_dti_tb";

Set the target language to SystemVerilog.

hdlcfg.TargetLanguage = "SystemVerilog";

Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti.

codegen -config hdlcfg mlhdlc_dti

Create a coder.FixptConfig object that has default settings and provide a test bench name.

fixptcfg = coder.config("fixpt"); fixptcfg.TestBenchName = "mlhdlc_sfir_tb";

Create a coder.HdlConfig object that has default settings and set enable rate.

hdlcfg = coder.config("hdl"); % Create a default "hdl" config hdlcfg.EnableRate = "DUTBaseRate";

Instruct MATLAB to generate a cosim test bench and a FIL test bench. Specify an FPGA board name.

hdlcfg.GenerateCosimTestBench = true; hdlcfg.FILBoardName = "Xilinx Virtex-5 XUPV5-LX110T development board"; hdlcfg.GenerateFILTestBench = true;

Perform code generation, Cosim test bench generation, and FIL test bench generation.

codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_sfir

Version History

Introduced in R2014b