Synthesis Tool - Specify the synthesis tool for targeting the generated HDL code - MATLAB (original) (raw)

Main Content

Specify the synthesis tool for targeting the generated HDL code

Model Configuration Pane: Target

Description

Specify the synthesis tool for targeting the generated HDL code. To use HDL Coder™ with one of the supported third-party FPGA synthesis tools, add the tool to the system path using the hdlsetuptoolpath function. When you specify the Synthesis Tool, HDL Coder populates the Family,Device,Package, andSpeed with default values for that tool. The Tool Path andTool Version display the synthesis tool path and tool version respectively of theSynthesis Tool that you specify.

Settings

No synthesis tool specified (Default) | Xilinx Vivado | Xilinx ISE | Altera Quartus II | Microchip Libero SoC | Intel Quartus Pro

The options are:

No synthesis tool specified

Select this option if you do not want to perform logic synthesis. You can generate HDL code from your design.

Xilinx Vivado

Specify Xilinx® Vivado as the synthesis tool.

Xilinx ISE

Specify Xilinx ISE as the synthesis tool.

Altera Quartus II

Specify Altera® Quartus II as the synthesis tool.

Microchip Libero SoC

Specify Microchip Libero® SoC as the synthesis tool.

Intel Quartus Pro

Specify Intel® Quartus® Pro as the synthesis tool.

If your synthesis tool is not one of the Synthesis tool options, see Synthesis Tool Path Setup.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify Altera Quartus II as theSynthesisTool when you generate HDL code for thesymmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the parameter as an argument to the makehdl function.
  makehdl('sfir_fixed/symmetric_fir', ...
  'SynthesisTool','Altera Quartus II')
• When you usehdlset_param, you can set the parameter on the model and then generate HDL code usingmakehdl.
  hdlset_param('sfir_fixed','SynthesisTool','Altera Quartus II')
  makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Restrictions

When you specify the target language to SystemVerilog, do not select Xilinx ISE as Synthesis tool. Xilinx ISE does not support SystemVerilog HDL language.

Version History

Introduced in R2014a