Tapped Delay Enabled Resettable Synchronous - Delay scalar signal multiple sample periods and output

  all delayed versions when external Enable signal is true and
  external Reset signal is false - Simulink ([original](https://www.mathworks.com/help/hdlcoder/ref/tappeddelayenabledresettablesynchronous.html)) ([raw](?raw))

Main Content

Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false

Since R2023a

Libraries:
HDL Coder / Discrete

Description

The Tapped Delay Enabled Resettable Synchronous block delays an input by the specified number of sample periods. The block returns an output signal for each delay when external Enable signal E is true and external Reset signalR is false.

For example, when you specify Number of delays as4 and Order output starting with asOldest, the block returns four signals, the first delayed by four sample periods, the second delayed by three, and so on. Use this block to discretize a signal in time domain or resample a signal.

Output Vector Order

The block accepts one scalar input and generates an output vector that contains data for each incremental delay. Specify the order of the delayed signals in the output vector with theOrder output vector starting with parameter:

Oldest orders the output vector starting with the oldest delay version and ending with the newest delay version.
Newest orders the output vector starting with the newest delay version and ending with the oldest delay version.

Specify the output vector for the first sampling period with the Initial condition parameter. Careful selection of this parameter can mitigate unwanted output behavior.

Synchronous State Control

The block uses synchronous state control semantics. When you use this block in your model and generate HDL code by using HDL Coder™, your model generates cleaner HDL code and uses fewer hardware resources due to the Synchronous behavior of the block.

Examples

Limitations

The block does not support vector inputs on the Enable port.
You cannot use the block inside Enabled Subsystem, Triggered Subsystem, or Resettable Subsystem blocks that useClassic semantics. The Subsystem must useSynchronous semantics.

Ports

Input

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Input signal to delay.

The block accepts the Enable signal of the data types listed below. For more information, see Data Types Supported by Simulink.

When the Enable signal is false and Reset signal is false, the state and output signal hold the previous value. The Enable signal is true when E input is not zero and false when E input is zero.

The block accepts the Reset signal of the data types listed below. For more information, see Data Types Supported by Simulink.

When the Reset signal is true, the state and output signal take the value of the Initial condition parameter. The Reset signal is true when R is not zero and false when R is zero.

Output

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All versions of the delayed input signal. Use theOrder output vector starting with parameter to specify the order of delayed signals in the output vector.

Parameters

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Specify the initial output of the simulation. The Initial condition parameter is converted from a double to the input data type offline using round-to-nearest and saturation.

Limitations

The initial condition of this block cannot be inf orNaN.

Programmatic Use

Block Parameter: vinit
Type: character vector
Values: scalar
Default: '0.0'

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

Programmatic Use

Block Parameter: samptime
Type: character vector
Values: scalar \| vector
Default: '-1'

Specify the number of discrete-time operators as a positive scalar, or-1 for inherited.

A value of -1 instructs the block to inherit the number of delays by backpropagation. Each delay is equivalent to the z-1 discrete-time operator, which the Unit Delay block represents.

Programmatic Use

Block Parameter: NumDelays
Type: character vector
Values: positive scalar \| -1 (inherited)
Default: '4'

Specify whether to output the oldest delay version first, or the newest delay version first.

Programmatic Use

Block Parameter: DelayOrder
Type: character vector
Values: 'Oldest' \| 'Newest'
Default: 'Oldest'

Select this check box to include the current input in the output vector.

Programmatic Use

Block Parameter: includeCurrent
Type: character vector
Values: 'off' \| 'on'
Default: 'off'

Extended Capabilities

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HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, see OutputPipeline.
ResetType	Suppress reset logic generation. The default is default, which generates reset logic. See also ResetType.

Complex Data Support

This block supports code generation for complex signals.

Version History

Introduced in R2023a