Generate Reset for Timing Controller - MATLAB & Simulink (original) (raw)

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You can generate a reset port for the timing controller, which generates the clock, clock enable, and reset signals in a multirate DUT. In the generated code, the reset for the timing controller is a DUT input port.

Requirements for Timing Controller Reset Port Generation

Your design must use single-clock mode. That is, theClockInputs property value must be'Single'.

How to Generate Reset for Timing Controller

To generate a reset port for the timing controller, set theTimingControllerArch property to'resettable' using makehdl orhdlset_param.

To disable reset port generation for the timing controller, set theTimingControllerArch property to'default'.

For example, for a model, sfirfixed, specify a reset port for the timing controller by entering:

hdlset_param('sfir_fixed','TimingControllerArch','resettable')

Limitations for Timing Controller Reset Port Generation

The following workflows are not compatible with timing controller reset port generation:

• FPGA-in-the-Loop
• Custom IP core generation