RTL Design Methodology Guidelines - MATLAB & Simulink (original) (raw)
Main Content
HDL Coder™ conforms to the following RTL design methodology guidelines, and checks for modeling constructs that violate these rules. HDL Coder reports potential rule violations in the HDL coding standard report. To avoid these violations, see the rule recommendations.
3.A Guidelines for Creating Function Libraries
3.A.C Signal, Port Constraints - I
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.A.C.1 Warning | Verilog/SystemVerilog: The order of module port decalarations and instance port connections lists should be same as the order in the module port map. | HDL Coder preserves the order of module port declarations and instance port connections as they appear in the original Simulink® DUT. | No action required. |
| 3.A.C.4a Message | Verilog/VHDL/SystemVerilog: Define only one port or signal per line in I/O, reg, and wire declaration. | HDL Coder complies with this rule. | No action required. |
3.A.D Signal, Port Constraints - II
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.A.D.4–5 Warning | Verilog/VHDL/SystemVerilog: Multiple assignments should not be made in one line. | The generated HDL code contains multiple assignments in one line or lines greater than N characters. You have a name or identifier in your original design that contains more than N characters. | Shorten names in your design that are longer than N characters.You can also customize N by using the LineLength property of the HDL coding standard customization object.HDL Coder folds the long lines in the design only so far as the HDL code syntax is not broken. |
| Verilog/VHDL/SystemVerilog: The maximum number of characters in one line should not be more than N. |
3.A.F Generic Usage Constraints
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.A.F.1 Reference | Verilog/SystemVerilog: Generic should be used in conditional expression of if generate statement. | HDL Coder does not generate if-generate statements, but can generate for-generate statements in the generated HDL code. | No action required. |
3.B Guidelines for Using Function Libraries
3.B.B Parameters, Constant Constraints
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.B.B.2b-4 Message | Verilog/SystemVerilog: Define macros should be read using include files. Include files must be specified with more than 1 level higher relative path. | HDL Coder does not generate macros in the HDL code. | No action required. |
| 3.B.B.5–7 Message | Verilog/SystemVerilog: Text macros should not be nested, and constants should be defined using parameters only. | HDL Coder does not generate macros in the HDL code. | No action required. |
3.B.C Port Constraints
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.B.C.1 Message | Verilog/VHDL/SystemVerilog: Port/Generic connections in instantiations must be made by named association rather than position association. | HDL Coder preserves the association of ports, so that it complies with this rule. | No action required. |
| 3.B.C.2 Message | Verilog/SystemVerilog: Bit-width of the component port and its connected net must match. | HDL Coder enforces type and bit-width matching, so that it complies with this rule. | No action required. |
| 3.B.C.3 Message | VHDL: Do not use entity instantiation in the design. | HDL Coder does not use entity instantiation in the design. The generated HDL code is generic and reusable. | No action required. |
3.B.D Generic Constraints
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.B.D.1 Error | Verilog/VHDL/SystemVerilog: Non-integer type used in the declaration of a generic may be unsynthesizable. | The generated HDL code contains a noninteger data type. | If you have floating-point data types in your design, you can map them to HDL Coder native floating-point libraries so that the generated code does not use floating-point data types.Alternatively, modify your design so that it does not use floating-point data types.You can disable this rule checking by using theNonIntegerTypes property of the HDL coding standard customization object. |
| 3.B.D.3 Error | Verilog/SystemVerilog: Do not use defparam statements. | HDL Coder complies with this rule. | No action required. |
3.C Guidelines for Test Facilitation Design
3.C.A Clock Constraints - I
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.C.A.1–4 Error | Verilog/VHDL/SystemVerilog: Internal clocks and aynschronous sets/resets must be controllable from external pins. | In the generated HDL code, you can control clocks from external pins. If you have a triggered subsystem and enableTriggerAsClock, then the trigger signal becomes a clock signal that you can control from external pins.For reset signals that you model in Simulink, the generated VHDL code can have a load port, which is a primary input in the generated code. | To avoid this rule violation, disable theTriggerAsClock. |
3.C.B Black Box Constraints
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.C.B.3 Error | Verilog/VHDL/SystemVerilog: Do not connect the outputs of a black box to clock, reset, or tristate enable pins. | HDL Coder connects the clock bundle to the entity or blackbox and does not modify it, so the generated code complies with this rule. | No action required. |
3.C.C Clock Constraints - II
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.C.C.1 Error | Verilog/VHDL/SystemVerilog: A clock must not be connected to the D input of a flip-flop. | HDL Coder does not use clock as data. | No action required. |
3.C.F Clock Constraints - III
| Rule / Severity | Message | Problem | Recommendations |
|---|---|---|---|
| 3.C.F.2 Error | Verilog/VHDL/SystemVerilog: Do not mix clock and reset lines. | HDL Coder connects the clock bundle to the entity or blackbox and does not modify it, so the generated code complies with this rule. | No action required. |