Signal and Data Type Support - MATLAB & Simulink (original) (raw)

HDL Coder™ supports code generation for Simulink® signal types and data types with a few special cases.

Buses

If your DUT or other blocks in your model have many input or output signals, you can create bus signals to improve the readability of your model. A bus signal or bus is a composite signal that consists of other signals that are called elements.

You can generate HDL code for designs that use virtual and nonvirtual buses. For example, you can generate code for designs that contain:

• DUT subsystem ports connected to buses.
• Simulink and Stateflow® blocks that support buses and HDL code generation.

Supported Blocks with Buses

Bus-capable blocks are blocks that can accept bus signals as input and produce bus signals as outputs. For a list of bus-capable blocks that Simulink supports, see Bus-Capable Blocks. HDL Coder supports code generation for bus-capable blocks in the HDL Coder block library. For more details, see the "HDL Code Generation" section of each block page. The supported blocks include:

• Bus Assignment
• Bus Creator
• Bus Selector
• Constant
• Delay
• Multiport Switch
• Rate Transition
• Signal Conversion
• Signal Specification
• Switch
• Unit Delay
• Vector Concatenate
• Zero-Order Hold

In addition, subsystems, models, and these user-defined functions support buses for simulation and HDL code generation:

• Subsystem
• Model references, see Model Referencing for HDL Code Generation.
• StateflowChart (Stateflow)
• MATLAB Function blocks
• MATLAB System blocks
• Vision HDL Toolbox™ blocks that accept a pixelcontrol bus for control input

Bus Support Limitations

You cannot generate code for designs that use:

• A Black box model reference connected to a bus.

Enumerations

You can generate code for Simulink, MATLAB®, or Stateflow enumerations within your design.

Requirements

• The enumeration strings must have unique names and must not use a reserved keyword in the Verilog®, SystemVerilog or VHDL language.
• If your target language is Verilog or SystemVerilog, all enumeration member names must be unique within the design.

Restrictions

Enumerations at the top-level DUT ports are not supported with the following workflows or verification methods:

• IP Core Generation workflow
• Simulink Real-Time FPGA I/O workflow
• FPGA-in-the-loop
• HDL Cosimulation

Matrices

You can use matrix types with these blocks in your design. For more details, see the "HDL Code Generation" section of each block page.

Unsupported Signal and Data Types

• Arrays stored in row-major layout are not supported for HDL code generation
• Variable-size signals are not supported for code generation.
• The Dataset objects set to timetable are not supported for HDL code generation. For more information, see Dataset signal format

See Also

Topics

• Generating HDL Code for Subsystems with Array of Buses
• Signal Types
• About Data Types in Simulink
• Composite Signals
• Use Enumerated Data in Simulink Models
• Enumerated Data (Stateflow)