Add X86_FEATURE_ZEN5 — Linux Tip Commits (original) (raw)

[tip: x86/urgent] x86/CPU/AMD: Add X86_FEATURE_ZEN5

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The following commit has been merged into the x86/urgent branch of tip:

Commit-ID: 3e4147f33f8b647775357bae0248b9a2aeebfcd2 Gitweb: https://git.kernel.org/tip/3e4147f33f8b647775357bae0248b9a2aeebfcd2 Author: Borislav Petkov (AMD) <bp@xxxxxxxxx> AuthorDate: Thu, 04 Jan 2024 21:11:37 +01:00 Committer: Borislav Petkov (AMD) <bp@xxxxxxxxx> CommitterDate: Tue, 23 Jan 2024 11:06:18 +01:00

x86/CPU/AMD: Add X86_FEATURE_ZEN5

Add a synthetic feature flag for Zen5.

arch/x86/include/asm/cpufeatures.h | 4 +--- arch/x86/kernel/cpu/amd.c | 25 +++++++++++++++++++++---- 2 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 29cb275..fdf723b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -81,10 +81,8 @@ #define X86_FEATURE_K6_MTRR ( 332+ 1) / AMD K6 nonstandard MTRRs / #define X86_FEATURE_CYRIX_ARR ( 332+ 2) /* Cyrix ARRs (= MTRRs) / #define X86_FEATURE_CENTAUR_MCR ( 332+ 3) /* Centaur MCRs (= MTRRs) */

-/* CPU types for specific tunings: / #define X86_FEATURE_K8 ( 332+ 4) /* "" Opteron, Athlon64 / -/ FREE, was #define X86_FEATURE_K7 ( 332+ 5) "" Athlon / +#define X86_FEATURE_ZEN5 ( 332+ 5) / "" CPU based on Zen5 microarchitecture / #define X86_FEATURE_P3 ( 332+ 6) /* "" P3 / #define X86_FEATURE_P4 ( 332+ 7) /* "" P4 / #define X86_FEATURE_CONSTANT_TSC ( 332+ 8) /* TSC ticks at a constant rate */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 9f42d1c..bc49e3b 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -538,7 +538,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)

 /* Figure out Zen generations: */
 switch (c->x86) {

@@ -554,8 +554,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) goto warn; } break; - } - case 0x19: { + + case 0x19: switch (c->x86_model) { case 0x00 ... 0x0f: case 0x20 ... 0x5f: @@ -569,7 +569,17 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) goto warn; } break; - } + + case 0x1a: + switch (c->x86_model) { + case 0x00 ... 0x0f: + setup_force_cpu_cap(X86_FEATURE_ZEN5); + break; + default: + goto warn; + } + break; + default: break; } @@ -1039,6 +1049,11 @@ static void init_amd_zen4(struct cpuinfo_x86 *c) msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); }

+static void init_amd_zen5(struct cpuinfo_x86 *c) +{ + init_amd_zen_common(); +} + static void init_amd(struct cpuinfo_x86 *c) { u64 vm_cr; @@ -1084,6 +1099,8 @@ static void init_amd(struct cpuinfo_x86 *c) init_amd_zen3(c); else if (boot_cpu_has(X86_FEATURE_ZEN4)) init_amd_zen4(c); + else if (boot_cpu_has(X86_FEATURE_ZEN5)) + init_amd_zen5(c);

 /*
  * Enable workaround for FXSAVE leak on CPUs

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