hierarchy - check, expand and clean up design hierarchy (original) (raw)
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yosys> help hierarchyΒΆ
hierarchy [-check] [-top ]
hierarchy -generate
In parametric designs, a module might exists in several variations with different parameter values. This pass looks at all modules in the current design and re-runs the language frontends for the parametric modules as needed. It also resolves assignments to wired logic data types (wand/wor), resolves positional module parameters, unrolls array instances, and more.
also check the design hierarchy. this generates an error when an unknown module is used as cell type.
like -check, but also throw an error if blackbox modules are instantiated, and throw an error if the design has no top module.
like -simcheck, but allow smtlib2_module modules.
by default the hierarchy command will not remove library (blackbox) modules. use this option to also remove unused blackbox modules.
search for files named .v in the specified directory for unknown modules and automatically run read_verilog for each unknown module.
per default this pass also converts positional arguments in cells to arguments using port names. This option disables this behavior.
per default this pass adjusts the port width on cells that are module instances when the width does not match the module port. This option disables this behavior.
do not resolve input port default values
per default this pass sets the "keep" attribute on all modules that directly or indirectly display text on the terminal. This option disables this behavior.
per default this pass sets the "keep" attribute on all modules that directly or indirectly contain one or more formal properties. This option disables this behavior.
use the specified top module to build the design hierarchy. Modules outside this tree (unused modules) are removed.
when the -top option is used, the 'top' attribute will be set on the specified top module. otherwise a module with the 'top' attribute set will implicitly be used as top module, if such a module exists.
automatically determine the top of the design hierarchy and mark it.
elaborate the top module using this parameter value. Modules on which this parameter does not exist may cause a warning message to be output. This option can be specified multiple times to override multiple parameters. String values must be passed in double quotes (").
In -generate mode this pass generates blackbox modules for the given cell types (wildcards supported). For this the design is searched for cells that match the given types and then the given port declarations are used to determine the direction of the ports. The syntax for a port declaration is:
{i|o|io}[@<num>]:<portname>Input ports are specified with the 'i' prefix, output ports with the 'o' prefix and inout ports with the 'io' prefix. The optional specifies the position of the port in the parameter list (needed when instantiated using positional arguments). When is not specified, the can also contain wildcard characters.
This pass ignores the current selection and always operates on all modules in the current design.