Circuit extraction (original) (raw)
The electric circuit extraction or simply circuit extraction, also netlist extraction, is the translation of an integrated circuit layout back into the electrical circuit (netlist) it is intended to represent. This extracted circuit is needed for various purposes including circuit simulation, static timing analysis, signal integrity, power analysis and optimization, and logic to layout comparison. Each of these functions require a slightly different representation of the circuit, resulting in the need for multiple layout extractions. In addition, there may be a postprocessing step of converting the device-level circuit into a purely digital circuit, but this is not considered part of the extraction process.
| Property | Value |
|---|---|
| dbo:abstract | The electric circuit extraction or simply circuit extraction, also netlist extraction, is the translation of an integrated circuit layout back into the electrical circuit (netlist) it is intended to represent. This extracted circuit is needed for various purposes including circuit simulation, static timing analysis, signal integrity, power analysis and optimization, and logic to layout comparison. Each of these functions require a slightly different representation of the circuit, resulting in the need for multiple layout extractions. In addition, there may be a postprocessing step of converting the device-level circuit into a purely digital circuit, but this is not considered part of the extraction process. The detailed functionality of an extraction process will depend on its system environment. The simplest form of extracted circuit may be in the form of a netlist, which is formatted for a particular simulator or analysis program. A more complex extraction may involve writing the extracted circuit back into the original database containing the physical layout and the logic diagram. In this case, by associating the extracted circuit with the layout and the logic network, the user can cross-reference any point in the circuit to its equivalent points in the logic and layout (cross-probing). For simulation or analysis, various formats of netlist can then be generated using programs that read the database and generate the appropriate text information. In extraction, it is often helpful to make an (informal) distinction between designed devices, which are devices that are deliberately created by the designer, and parasitic devices, which were not explicitly intended by the designer but are inherent in the layout of the circuit. Primarily there are three different parts to the extraction process. These are designed device extraction, interconnect extraction, and parasitic device extraction. These parts are inter-related since various device extractions can change the connectivity of the circuit, e.g., resistors (whether designed or parasitic) convert single nets into multiple electrical nodes. Usually one level of interconnect extraction is used with designed device extraction to provide a circuit for simulation or gate-level reduction, and a second level of interconnect extraction is used with parasitic device extraction to provide a circuit for timing analysis. (en) |
| dbo:wikiPageID | 3430375 (xsd:integer) |
| dbo:wikiPageLength | 3217 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1070872804 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:Electromagnetic_field_solver dbr:Electronic_design_automation dbc:Electronic_design_automation dbr:Integrated_circuit_layout dbr:SPICE dbr:Netlist dbr:Electrical_circuit dbr:Power_optimization_(EDA) dbr:Formal_equivalence_checking dbr:Digital_circuit dbc:Integrated_circuits dbc:Electronic_design dbc:Electronic_engineering dbr:Static_timing_analysis dbr:Signal_integrity |
| dbp:wikiPageUsesTemplate | dbt:ISBN dbt:Short_description dbt:Use_American_English |
| dct:subject | dbc:Electronic_design_automation dbc:Integrated_circuits dbc:Electronic_design dbc:Electronic_engineering |
| gold:hypernym | dbr:Translation |
| rdf:type | yago:Artifact100021939 yago:Circuit103033362 yago:ComputerCircuit103084420 yago:Device103183080 yago:ElectricalDevice103269401 yago:Instrumentality103575240 yago:IntegratedCircuit103577090 yago:Object100002684 yago:PhysicalEntity100001930 yago:WikicatIntegratedCircuits dbo:Book yago:Whole100003553 |
| rdfs:comment | The electric circuit extraction or simply circuit extraction, also netlist extraction, is the translation of an integrated circuit layout back into the electrical circuit (netlist) it is intended to represent. This extracted circuit is needed for various purposes including circuit simulation, static timing analysis, signal integrity, power analysis and optimization, and logic to layout comparison. Each of these functions require a slightly different representation of the circuit, resulting in the need for multiple layout extractions. In addition, there may be a postprocessing step of converting the device-level circuit into a purely digital circuit, but this is not considered part of the extraction process. (en) |
| rdfs:label | Circuit extraction (en) |
| owl:sameAs | freebase:Circuit extraction yago-res:Circuit extraction wikidata:Circuit extraction https://global.dbpedia.org/id/f8p1 |
| prov:wasDerivedFrom | wikipedia-en:Circuit_extraction?oldid=1070872804&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:Circuit_extraction |
| is dbo:wikiPageRedirects of | dbr:Layout_extraction dbr:Netlist_extraction |
| is dbo:wikiPageWikiLink of | dbr:Application-specific_integrated_circuit dbr:List_of_books_in_computational_geometry dbr:NanGate dbr:Process_corners dbr:Layout_extraction dbr:Netlist_extraction |
| is foaf:primaryTopic of | wikipedia-en:Circuit_extraction |