Clock domain crossing (original) (raw)
In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary. A synchronous system is composed of a single electronic oscillator that generates a clock signal, and its clock domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements.
| Property | Value |
|---|---|
| dbo:abstract | In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary. A synchronous system is composed of a single electronic oscillator that generates a clock signal, and its clock domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements. Because of speed-of-light delays, timing skew, etc., the size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock. In early computers, typically all the digital logic ran in a single clock domain. Because of transmission line loss and distortion it is difficult to carry digital signals above 66 MHz on standard PCB traces (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a phase-locked loop (PLL) or other on-chip oscillator, keeping the fastest signals on-chip. At first, each CPU chip ran in its own single clock domain, and the rest of the digital logic of the computer ran in another slower clock domain. A few modern CPUs have such a high speed clock, that designers are forced to create several different clock domains on a single CPU chip. Different clock domains have clocks which have a different frequency, a different phase (due to either differing clock latency or a different clock source), or both. Either way the relationship between the clock edges in the two domains cannot be relied upon. Synchronizing a single bit signal to a clock domain with a higher frequency can be accomplished by registering the signal through a flip-flop that is clocked by the source domain, thus holding the signal long enough to be detected by the higher frequency clocked destination domain. CDC metastability issues can occur between asynchronous clock domains; this is in contrast to reset domain crossing metastability, which can occur between synchronous & asynchronous clock domains. To avoid issues with CDC metastability in the destination clock domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination domain. Synchronizing a single bit signal traversing into clock domain with a slower frequency is more cumbersome. This typically requires a register in each clock domain with a form of feedback from the destination domain to the source domain, indicating that the signal was detected. Other potential clock domain crossing design errors include glitches and data loss. In some cases, clock gating can result in two clock domains where the "slower" domain changes from one second to the next. (en) |
| dbo:wikiPageExternalLink | http://www.cadence.com/whitepapers/cdc_wp.pdf http://www.electronics-eetimes.com/documents/whitepapers/13-07/mentorpaper_32969_5-steps-to-quality-cdc-verification.pdf https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html https://web.archive.org/web/20070125072758/http:/www.cadence.com/whitepapers/cdc_wp.pdf https://web.archive.org/web/20150511034154/https:/filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html |
| dbo:wikiPageID | 5028779 (xsd:integer) |
| dbo:wikiPageLength | 7532 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1020529251 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:Cadence_Design_Systems dbr:Electronic_oscillator dbr:Metastability_(electronics) dbr:Virginia_Tech dbr:Combinational_logic dbc:Telecommunication_theory dbr:Mentor_Graphics dbr:Clock_skew dbr:Gray_code dbr:Clock_gating dbr:Clock_signal dbr:Phase-locked_loop dbr:Phase_(waves) dbr:Crosstalk_(electronics) dbr:Flip-flop_(electronics) dbr:Glitch dbr:Globally_asynchronous_locally_synchronous dbr:Digital_circuit dbr:Synchronous_circuit dbr:Asynchronous_array_of_simple_processors dbr:Asynchronous_communication dbr:EeNews_Europe dbc:Electronic_circuit_verification dbr:Speed_of_light dbr:Printed_circuit_board dbr:System_on_a_chip dbr:Signal_integrity dbr:Transmission_line dbr:Source-synchronous dbr:Metastability_in_electronics dbr:Clock_domain dbr:Clock_frequency |
| dbp:cs1Dates | y (en) |
| dbp:date | May 2019 (en) |
| dbp:wikiPageUsesTemplate | dbt:Cite_web dbt:Reflist dbt:Section_link dbt:Use_dmy_dates dbt:When dbt:Which |
| dcterms:subject | dbc:Telecommunication_theory dbc:Electronic_circuit_verification |
| gold:hypernym | dbr:Traversal |
| rdfs:comment | In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary. A synchronous system is composed of a single electronic oscillator that generates a clock signal, and its clock domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements. (en) |
| rdfs:label | Clock domain crossing (en) |
| owl:sameAs | freebase:Clock domain crossing wikidata:Clock domain crossing https://global.dbpedia.org/id/4hw6Q |
| prov:wasDerivedFrom | wikipedia-en:Clock_domain_crossing?oldid=1020529251&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:Clock_domain_crossing |
| is dbo:wikiPageDisambiguates of | dbr:CDC_(disambiguation) |
| is dbo:wikiPageRedirects of | dbr:Clock_Domain_Crossing dbr:Clock_Domain_Crossing_Verification dbr:Clock_domain_change dbr:Clock_domain_crossing_verification dbr:CDC_check dbr:Multi_clock_crossing dbr:Multiple_clock_crossing |
| is dbo:wikiPageWikiLink of | dbr:Electronic_design_automation dbr:Network_on_a_chip dbr:CDC_(disambiguation) dbr:Clock_signal dbr:Clock_Domain_Crossing dbr:Clock_Domain_Crossing_Verification dbr:Logic_block dbr:FPGA_prototyping dbr:Globally_asynchronous_locally_synchronous dbr:Handel-C dbr:Field-programmable_gate_array dbr:Signoff_(electronic_design_automation) dbr:Clock_domain_change dbr:Clock_domain_crossing_verification dbr:CDC_check dbr:Multi_clock_crossing dbr:Multiple_clock_crossing |
| is foaf:primaryTopic of | wikipedia-en:Clock_domain_crossing |