Compressed instruction set (original) (raw)
A compressed instruction set, or simply compressed instructions, are a variation on a microprocessor's instruction set architecture (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed instructions are 16 bits long in a processor that would otherwise use 32-bit instructions. The 16-bit ISA is a subset of the full 32-bit ISA, not a separate instruction set. The smaller format requires some tradeoffs: generally, there are fewer instructions available, and fewer processor registers can be used.
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| dbo:abstract | A compressed instruction set, or simply compressed instructions, are a variation on a microprocessor's instruction set architecture (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed instructions are 16 bits long in a processor that would otherwise use 32-bit instructions. The 16-bit ISA is a subset of the full 32-bit ISA, not a separate instruction set. The smaller format requires some tradeoffs: generally, there are fewer instructions available, and fewer processor registers can be used. The concept was originally introduced by Hitachi as a way to improve the code density of their SuperH RISC processor design as it moved from 16-bit to 32-bit instructions in the SH-5 version. The new design had two instruction sets, one giving access to the entire ISA of the new design, and a smaller 16-bit set known as SHcompact that allowed programs to run in smaller amounts of main memory. As the memory of even the smallest systems is now orders of magnitude larger than the systems that spawned the concept, size is no longer the main concern. Today the advantage is that it reduces the number of accesses to main memory and thereby reduces energy use in mobile devices. Hitachi's patents were licensed by Arm Ltd. for their processors, where it was known as "Thumb". Similar systems are found in MIPS16e and PowerPC VLE. The original patents have expired and the concept can be found in a number of modern designs, including RISC-V, which was designed from the outset to use it. The introduction of 64-bit computing has led to the term no longer being as widely used; these processors generally use 32-bit instructions and are technically a form of compressed ISA, but as they are mostly modified versions of an older ISA from a 32-bit version of the same processor family; there is no real compression. (en) |
| dbo:wikiPageExternalLink | http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf https://antime.kapsi.fi/sega/files/h12p0.pdf https://www.embedded.com/introduction-to-arm-thumb/ https://people.cs.umass.edu/~verts/cmpsci201/spr_2004/Lecture_02_2004-01-30_The_6502_processor.pdf |
| dbo:wikiPageID | 67354180 (xsd:integer) |
| dbo:wikiPageLength | 12243 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1114187842 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:Benchmarking dbr:PowerPC dbr:Power_ISA dbr:Processor_register dbr:Minicomputer dbr:Opcode dbr:Hitachi dbr:Intel_8088 dbr:Zero_register dbr:Code_density dbr:Endianness dbr:Freescale_Semiconductor dbr:Mobile_device dbr:Most_significant_bit dbr:MIPS_architecture dbr:Static_random-access_memory dbr:Microcode dbr:64-bit_computing dbr:Byte dbc:Hitachi dbr:Logical_shift dbr:Addressing_mode dbr:DRAM dbr:Instruction_decoder dbr:Hexadecimal dbr:Backward_compatibility dbr:Arm_Ltd. dbc:Instruction_set_architectures dbr:Accumulator_(computing) dbr:Bit dbr:Instruction_set_architecture dbr:Microprocessor dbr:RISC-V dbr:SuperH dbr:Zero_page dbr:Instruction_cache dbr:RISC dbr:MOS_6502 dbr:Order-of-magnitude dbr:Variable_length_instruction_set dbr:Mainframe dbr:Main_memory |
| dbp:wikiPageUsesTemplate | dbt:= dbt:Cite_book dbt:Cite_conference dbt:Cite_web dbt:Code dbt:Reflist dbt:Sfn dbt:Short_description |
| dct:subject | dbc:Hitachi dbc:Instruction_set_architectures |
| rdfs:comment | A compressed instruction set, or simply compressed instructions, are a variation on a microprocessor's instruction set architecture (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed instructions are 16 bits long in a processor that would otherwise use 32-bit instructions. The 16-bit ISA is a subset of the full 32-bit ISA, not a separate instruction set. The smaller format requires some tradeoffs: generally, there are fewer instructions available, and fewer processor registers can be used. (en) |
| rdfs:label | Compressed instruction set (en) |
| owl:sameAs | wikidata:Compressed instruction set dbpedia-tr:Compressed instruction set https://global.dbpedia.org/id/Fx9Nx |
| prov:wasDerivedFrom | wikipedia-en:Compressed_instruction_set?oldid=1114187842&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:Compressed_instruction_set |
| is dbo:wikiPageRedirects of | dbr:Compressed_instructions |
| is dbo:wikiPageWikiLink of | dbr:V850 dbr:Iron_law_of_processor_performance dbr:Instruction_set_architecture dbr:RISC-V dbr:Reduced_instruction_set_computer dbr:SuperH dbr:Compressed_instructions |
| is foaf:primaryTopic of | wikipedia-en:Compressed_instruction_set |