Current-mode logic (original) (raw)
Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signalling of digital data . The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented. Typically, the generator is connected to the two sources of a pair of differential FETs, with the two paths being their two drains. Bipolar equivalents operate similarly, with the output being taken from the collectors of the BJT transistors.
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| dbo:abstract | Bei dem englischen Begriff Current Mode Logic (kurz: CML, deutsch Stromschaltlogik), auch englisch Source Coupled Logic (kurz: SCL, deutsch in etwa Source-gekoppelte Logik), handelt es sich in der Digitaltechnik um einen Schnittstellen-Standard für kabelbasierende Hochgeschwindigkeits-Datenübertragungen mit Bitraten zwischen 312,5 MBit/s bis 12,5 GBit/s. CML ist mit dem Übertragungsstandard Low Voltage Differential Signaling (LVDS) vergleichbar, weist allerdings für die verwendeten Kupferkabel einen fix definierten Leitungswellenwiderstand von 50 Ω auf. CML ist standardisiert im JEDEC-Standard JESD204. Im Rahmen von Netzwerkprotokollschicht-Modellen beschreibt CML die unterste physische Bitübertragungsschicht, nicht die darauf aufsetzenden höheren Protokoll-Schichten. CML findet Einsatz unter anderem bei Digital-Analog-Umsetzern und Analog-Digital-Umsetzern mit hohen Datenraten zur Datenanbindung an digitale Logikschaltungen wie Field Programmable Gate Arrays (FPGAs). Weitere Anwendungen sind Schnittstellen, die auf dem Transition-Minimized Differential Signaling (TMDS) basieren. Beispiele dafür sind Digital Visual Interface (DVI) und High-Definition Multimedia Interface (HDMI). CML verwendet eine differenzielle Übertragung auf Leitungen definierter Wellenimpedanz. Als aktive Bauelemente kommen Bipolartransistoren im linearen Betriebsbereich zum Einsatz; die Spannungsdifferenz zwischen den beiden Leitungen beträgt im Nennwert 800 mV. (de) Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signalling of digital data . The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented. Typically, the generator is connected to the two sources of a pair of differential FETs, with the two paths being their two drains. Bipolar equivalents operate similarly, with the output being taken from the collectors of the BJT transistors. As a differential PCB-level interconnect, it is intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standard printed circuit boards. The transmission is point-to-point, unidirectional, and is usually terminated at the destination with 50 Ω resistors to Vcc on both differential lines. CML is frequently used in interfaces to fiber optic components. The principle difference between CML and ECL as a link technology is the output impedance of the driver stage: the emitter follower of ECL has a low resistance of around 5 ohms whereas CML connects to the drains of the driving transistors, that have a high impedance, and so the impedance of the pull up/down network (typically 50 ohm resistive) is the effective output impedance. Having a drive impedance closer to the driven line's characteristic impedance greatly reduces undesirable ringing. CML signals have also been found useful for connections between modules. CML is the physical layer used in DVI, HDMI and FPD-Link III video links, the interfaces between a display controller and a monitor. In addition, CML has been widely used in high-speed integrated systems, such as telecommunication systems such as: serial data transceivers, and frequency synthesizers. (en) |
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| rdfs:comment | Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signalling of digital data . The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented. Typically, the generator is connected to the two sources of a pair of differential FETs, with the two paths being their two drains. Bipolar equivalents operate similarly, with the output being taken from the collectors of the BJT transistors. (en) Bei dem englischen Begriff Current Mode Logic (kurz: CML, deutsch Stromschaltlogik), auch englisch Source Coupled Logic (kurz: SCL, deutsch in etwa Source-gekoppelte Logik), handelt es sich in der Digitaltechnik um einen Schnittstellen-Standard für kabelbasierende Hochgeschwindigkeits-Datenübertragungen mit Bitraten zwischen 312,5 MBit/s bis 12,5 GBit/s. CML ist mit dem Übertragungsstandard Low Voltage Differential Signaling (LVDS) vergleichbar, weist allerdings für die verwendeten Kupferkabel einen fix definierten Leitungswellenwiderstand von 50 Ω auf. CML ist standardisiert im JEDEC-Standard JESD204. (de) |
| rdfs:label | Current Mode Logic (de) Current-mode logic (en) |
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