Machine Check Architecture (original) (raw)
In computing, Machine Check Architecture (MCA) is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system. Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.
| Property | Value |
|---|---|
| dbo:abstract | In computing, Machine Check Architecture (MCA) is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system. Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected. (en) |
| dbo:wikiPageExternalLink | http://www.mcelog.org/ http://www.microsoft.com/whdc/system/platform/64bit/MCAsupport.mspx |
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| dbo:wikiPageWikiLink | dbr:Error_detection_and_correction dbr:Computing dbr:Translation_lookaside_buffer dbr:CPU_cache dbr:AMD dbc:X86_architecture dbr:Reliability,_availability_and_serviceability dbc:Computer_architecture dbr:High_availability dbr:Intel dbr:Operating_system dbr:CPU dbr:Machine-check_exception dbr:Model-specific_register dbr:Windows_Hardware_Error_Architecture |
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| dct:subject | dbc:X86_architecture dbc:Computer_architecture |
| gold:hypernym | dbr:Mechanism |
| rdf:type | dbo:Organisation |
| rdfs:comment | In computing, Machine Check Architecture (MCA) is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system. Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected. (en) |
| rdfs:label | Machine Check Architecture (en) |
| owl:sameAs | freebase:Machine Check Architecture wikidata:Machine Check Architecture https://global.dbpedia.org/id/4qxhz |
| prov:wasDerivedFrom | wikipedia-en:Machine_Check_Architecture?oldid=1113651087&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:Machine_Check_Architecture |
| is dbo:wikiPageDisambiguates of | dbr:MCA |
| is dbo:wikiPageRedirects of | dbr:Machine_check_architecture |
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| is dbp:extensions of | dbr:X86 |
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