OpenPIC and MPIC (original) (raw)
In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors. The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995. No x86 motherboard was released with OpenPIC however. After the OpenPIC's failure in the x86 market, AMD licensed the Intel APIC Architecture for its AMD Athlon and later processors.
| Property | Value |
|---|---|
| dbo:abstract | In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors. The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995. No x86 motherboard was released with OpenPIC however. After the OpenPIC's failure in the x86 market, AMD licensed the Intel APIC Architecture for its AMD Athlon and later processors. IBM however developed their Multiprocessor Interrupt Controller (MPIC) based on the OpenPIC register specification. In the reference IBM design, the processors share the MPIC over a DCR bus, with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources. Through various implementations, the MPIC was included in PowerPC reference designs and some retail computers. IBM used a MPIC based on OpenPIC 1.0 in their RS/6000 F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual 8259 on their PCI-ISA bridges. An IBM MPIC was also used in the RS/6000 7046 Model B50. The Apple Hydra (MIO) chip (from the 1990s classic Mac OS era) implemented a MPIC alongside a SCSI controller, ADB controller, GeoPort controller, and timers. The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the Common Hardware Reference Platform was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources. A MPIC was also incorporated in the newer K2 I/O controller used in the Power Mac G5s. Freescale also uses a MPIC ("compatible with the Open PIC") on all its PowerQUICC and QorIQ processors. The Linux Kernel-based Virtual Machine (KVM) supports a virtualized MPIC with up to 256 interrupts, based on the Freescale variants. (en) |
| dbo:wikiPageExternalLink | http://opensource.apple.com/source/AppleMPIC/ |
| dbo:wikiPageID | 41919547 (xsd:integer) |
| dbo:wikiPageLength | 4958 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1102922937 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:PowerPC dbr:Power_Mac_G5 dbr:Programmable_Interrupt_Controller dbc:Macintosh_platform dbr:PowerQUICC dbr:Compaq dbr:GeoPort dbr:QorIQ dbr:Classic_Mac_OS dbr:CoreConnect dbr:Apple_Desktop_Bus dbr:Apple_Inc. dbc:Freescale_Semiconductor dbr:Common_Hardware_Reference_Platform dbr:AMD dbr:AMD_Athlon dbr:Cyrix dbc:Advanced_Micro_Devices_platforms dbc:Motherboard dbr:Advanced_Programmable_Interrupt_Controller dbc:Interrupts dbr:Kernel-based_Virtual_Machine dbc:IBM_computer_hardware dbr:IBM dbr:Intel dbr:Intel_486 dbr:Intel_APIC_Architecture dbr:RS/6000 dbr:SCSI dbr:8259 dbr:Freescale dbr:Multiprocessor dbr:Mac_I/O |
| dbp:wikiPageUsesTemplate | dbt:Reflist |
| dct:subject | dbc:Macintosh_platform dbc:Freescale_Semiconductor dbc:Advanced_Micro_Devices_platforms dbc:Motherboard dbc:Interrupts dbc:IBM_computer_hardware |
| rdfs:comment | In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors. The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995. No x86 motherboard was released with OpenPIC however. After the OpenPIC's failure in the x86 market, AMD licensed the Intel APIC Architecture for its AMD Athlon and later processors. (en) |
| rdfs:label | OpenPIC and MPIC (en) |
| owl:sameAs | freebase:OpenPIC and MPIC wikidata:OpenPIC and MPIC https://global.dbpedia.org/id/exeS |
| prov:wasDerivedFrom | wikipedia-en:OpenPIC_and_MPIC?oldid=1102922937&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:OpenPIC_and_MPIC |
| is dbo:wikiPageRedirects of | dbr:OpenPIC_and_IBM_MPIC dbr:OpenPIC dbr:MultiProcessor_Interrupt_Controller |
| is dbo:wikiPageWikiLink of | dbr:OpenPIC_and_IBM_MPIC dbr:Advanced_Programmable_Interrupt_Controller dbr:OpenPIC dbr:MultiProcessor_Interrupt_Controller |
| is foaf:primaryTopic of | wikipedia-en:OpenPIC_and_MPIC |