Universal Verification Methodology (original) (raw)
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, Synopsys, Xilinx Simulator(XSIM).
| Property | Value |
|---|---|
| dbo:abstract | The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, Synopsys, Xilinx Simulator(XSIM). (en) 通用验证方法学（英語：Universal Verification Methodology, UVM）是一个以SystemVerilog类库为主体的验证平台开发框架，验证工程师可以利用其可重用组件构建具有标准化层次结构和接口的功能验证环境。它是第一个由电子设计自动化领域三巨头（Cadence、Synopsys和Mentor Graphics）联合支持的验证方法学，其最新版本为1.2版。 (zh) |
| dbo:wikiPageExternalLink | http://www.edaplayground.com http://eda-playground.readthedocs.org/en/latest/_static/uvm-1.2/index.html http://www.accellera.org/community/uvm/ http://www.accellera.org/resources/videos/uvmreadysetdeploy/ http://www.doulos.com/knowhow/sysverilog/uvm/tutorial_0/ https://www.youtube.com/watch%3Fv=V2l4lBlsh7k&list=SPScWdLzHpkAdYPk_jgxRgOPisTm3-7U6A |
| dbo:wikiPageID | 26230197 (xsd:integer) |
| dbo:wikiPageLength | 8635 (xsd:nonNegativeInteger) |
| dbo:wikiPageRevisionID | 1077058314 (xsd:integer) |
| dbo:wikiPageWikiLink | dbr:Cadence_Design_Systems dbr:Electronic_design_automation dbc:Electronic_design_automation dbr:Integrated_circuit dbr:Mentor_Graphics dbr:Object_(computer_science) dbr:Open_Verification_Methodology dbr:Accellera dbr:E_(verification_language) dbr:ERM_(e_Reuse_Methodology) dbr:SystemVerilog dbr:Factory_(object-oriented_programming) |
| dbp:wikiPageUsesTemplate | dbt:Primary_sources dbt:Reflist |
| dct:subject | dbc:Electronic_design_automation |
| gold:hypernym | dbr:Methodology |
| rdf:type | dbo:Software |
| rdfs:comment | The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, Synopsys, Xilinx Simulator(XSIM). (en) 通用验证方法学（英語：Universal Verification Methodology, UVM）是一个以SystemVerilog类库为主体的验证平台开发框架，验证工程师可以利用其可重用组件构建具有标准化层次结构和接口的功能验证环境。它是第一个由电子设计自动化领域三巨头（Cadence、Synopsys和Mentor Graphics）联合支持的验证方法学，其最新版本为1.2版。 (zh) |
| rdfs:label | Universal Verification Methodology (en) 通用验证方法学 (zh) |
| owl:sameAs | freebase:Universal Verification Methodology wikidata:Universal Verification Methodology dbpedia-zh:Universal Verification Methodology https://global.dbpedia.org/id/4wjpr |
| prov:wasDerivedFrom | wikipedia-en:Universal_Verification_Methodology?oldid=1077058314&ns=0 |
| foaf:isPrimaryTopicOf | wikipedia-en:Universal_Verification_Methodology |
| is dbo:wikiPageDisambiguates of | dbr:UVM_(disambiguation) |
| is dbo:wikiPageWikiLink of | dbr:List_of_acronyms:_U dbr:E_Reuse_Methodology dbr:Open_Verification_Methodology dbr:Siemens_EDA dbr:Accellera dbr:E_(verification_language) dbr:Aldec dbr:RISC-V dbr:UVM_(disambiguation) |
| is foaf:primaryTopic of | wikipedia-en:Universal_Verification_Methodology |