Real-Time and Embedded Systems Lab (original) (raw)

Jan ReinekeReal-Time and Embedded Systems Lab Saarland University Saarland Informatics CampusPhone: +49 681 302 4448eMail: Building: E 1 3 Room: 410Coordinates: N 49.257833° E 7.045144° Administrative Assistant: Sandra Neumann Phone: +49 681 302 3434 Building: E 1 3 Room: 430 Office Hour: Wednesday 16:00-17:00 (please send me an email, as I may be travelling; other times are possible)
I am looking for PhD students and postdocs to work on safety and security problems at the hardware-software interface! Possible research topics are flexible and include but are not limited to: Static program analysis of real-time and security properties Design of timing-predictable microarchitectures Design of secure microarchitectures Formal verification of hardware w.r.t. hardware-software contracts If you are interested, please feel free to . My work is generously supported by an ERC Advanced Grant. If you are interested in working with me and my group or if you are looking for a Bachelor or Master thesis topic, please feel free to stop by my office or to drop me an email.

Short CV

Jan Reineke is a professor of computer science at Saarland University. Before joining Saarland University in 2012, he has been a postdoctoral scholar at UC Berkeley in the Ptolemy group from 2009 to 2011. He completed his MSc and PhD in Computer Science at Saarland University in 2005 and 2008, respectively, and his BSc in Computing Science at the University of Oldenburg in 2003.

His research centers around problems at the boundary between hardware and software.

In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019, RTSS 2019).

Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector, S&P 2020), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (uops.info, ASPLOS 2019).

In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded ten outstanding paper awards and two best-paper nominations, most recently at RTAS (2025), DATE (2024), CCS (2023), RTSS (2023, 2019, 2018), Oakland (2021), and ECRTS (2017). In 2021, he was awarded an ERC Advanced Grant.

Selected Recent Publications

Conference and Workshop Papers

  1. A Unified Framework for Quantitative Cache Analysis (Best Student Paper Award award)
    S. Kahlen and J. Reineke
    RTAS, 2025
    [doi] [bib]
    @inproceedings{KahlenRTAS2025,
    title = {A Unified Framework for Quantitative Cache Analysis},
    author = {Kahlen, Sophie and Reineke, Jan},
    booktitle = {31st {IEEE} Real-Time and Embedded Technology and Applications Symposium, {RTAS} 2025, Irvine, CA, USA, May 6-9, 2025},
    doi = {10.1109/RTAS65571.2025.00018},
    pages = {54--67},
    publisher = {{IEEE}},
    timestamp = {Thu, 12 Jun 2025 14:48:52 +0200},
    url = {https://doi.org/10.1109/RTAS65571.2025.00018},
    year = {2025}
    }
  2. Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
    Z. Wang, G. Mohr, K. Gleissenthall, J. Reineke, and M. Guarnieri
    CCS, 2025
    [bib]
    @inproceedings{wang2025synthesis,
    title = {Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors},
    author = {Wang, Zilong and Mohr, Gideon and Gleissenthall, Klaus von and Reineke, Jan and Guarnieri, Marco},
    booktitle = {Proceedings of the 32nd ACM Conference on Computer and Communications Security},
    publisher = {ACM},
    series = {CCS 2025},
    year = {2025}
    }
  3. Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors (Best Paper Award Candidate award)
    G. Mohr, M. Guarnieri, and J. Reineke
    DATE, March 2024
    [bib]
    @inproceedings{Mohr24,
    title = {Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors},
    author = {Mohr, Gideon and Guarnieri, Marco and Reineke, Jan},
    booktitle = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2024},
    month = {Mar},
    organization = {IEEE},
    year = {2024}
    }
  4. Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis (Outstanding Paper Award award)
    V. Touzeau and J. Reineke
    RTSS, 2023
    [bib]
    @inproceedings{Touzeau23,
    title = {Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis},
    author = {Touzeau, Valentin and Reineke, Jan},
    booktitle = {2023 {IEEE} Real-Time Systems Symposium, {RTSS} 2023, Taipei, Taiwan, December 5-8, 2023},
    year = {2023}
    }
  5. Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts (Distinguished Paper Award at CCS 2023 and Intel Hardware Security Academic Award Finalist 2024award)
    Z. Wang, G. Mohr, K. Gleissenthall, J. Reineke, and M. Guarnieri
    CCS, 2023
    [bib]
    @inproceedings{wang2023specification,
    title = {Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts},
    author = {Wang, Zilong and Mohr, Gideon and Gleissenthall, Klaus von and Reineke, Jan and Guarnieri, Marco},
    booktitle = {Proceedings of the 30th ACM Conference on Computer and Communications Security},
    publisher = {ACM},
    series = {CCS 2023},
    year = {2023}
    }
  6. uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
    A. Abel and J. Reineke
    ICS, 2022
    [bib]
    @inproceedings{Abel22,
    title = {{uiCA}: Accurate Throughput Prediction of Basic Blocks on Recent {Intel} Microarchitectures},
    author = {Abel, Andreas and Reineke, Jan},
    booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual Event, USA, June 27-30, 2022},
    series = {ICS '22},
    editor = {Rauchwerger, Lawrence and Cameron, Kirk and Nikolopoulos, Dimitrios S. and Pnevmatikatos, Dionisios},
    pages = {1--12},
    publisher = {{ACM}},
    month = {June},
    year = {2022},
    url = {https://dl.acm.org/doi/pdf/10.1145/3524059.3532396}
    }
  7. Hardware-Software Contracts for Secure Speculation (Best Paper Award award)
    M. Guarnieri, B. Köpf, J. Reineke, and P. Vila
    S&P (Oakland), May 2021
    [bib]
    @inproceedings{Guarnieri21,
    title = {Hardware-Software Contracts for Secure Speculation},
    author = {Guarnieri, Marco and K{{"o}}pf, Boris and Reineke, Jan and Vila, Pepe},
    booktitle = {2021 {IEEE} Symposium on Security and Privacy, {SP} 2021, Proceedings, San Francisco, California, {USA}},
    month = {May},
    url = {https://arxiv.org/abs/2006.03841},
    year = {2021}
    }
  8. SPECTECTOR: Principled Detection of Speculative Information Flows
    M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sánchez
    S&P (Oakland), May 2020
    [pdf] [bib]
    @inproceedings{Guarnieri20,
    title = {{SPECTECTOR:} Principled Detection of Speculative Information Flows},
    author = {Guarnieri, Marco and K{{"o}}pf, Boris and Morales, Jos{{'e}} F. and Reineke, Jan and S{{'a}}nchez, Andr{{'e}}s},
    booktitle = {2020 {IEEE} Symposium on Security and Privacy, {SP} 2020, Proceedings, San Francisco, California, {USA}},
    month = {May},
    url = {https://spectector.github.io/papers/spectector.pdf},
    year = {2020}
    }
  9. uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
    A. Abel and J. Reineke
    ASPLOS, 2019
    [doi] [bib]
    @inproceedings{Abel19a,
    title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on {Intel} Microarchitectures},
    acmid = {3304062},
    address = {New York, NY, USA},
    author = {Abel, Andreas and Reineke, Jan},
    booktitle = {ASPLOS},
    doi = {10.1145/3297858.3304062},
    isbn = {978-1-4503-6240-5},
    location = {Providence, RI, USA},
    numpages = {14},
    pages = {673--686},
    publisher = {ACM},
    series = {ASPLOS '19},
    url = {http://doi.acm.org/10.1145/3297858.3304062},
    year = {2019}
    }
  10. Cache Persistence Analysis: Finally Exact (Best Paper Award award)
    G. Stock, S. Hahn, and J. Reineke
    RTSS, December 2019
    [bib]
    @inproceedings{Stock19,
    title = {Cache Persistence Analysis: Finally Exact},
    author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
    booktitle = {RTSS},
    month = {Dec},
    year = {2019}
    }
  11. Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award award)
    S. Hahn and J. Reineke
    RTSS, December 2018
    [pdf] [pdf slides] [bib]
    @inproceedings{Hahn18,
    title = {Design and Analysis of {SIC}: A Provably Timing-Predictable Pipelined Processor Core},
    author = {Hahn, Sebastian and Reineke, Jan},
    booktitle = {RTSS},
    month = {Dec},
    year = {2018}
    }

Publications

A list of all of my publications can be found here and on DBLP.

Recent and Upcoming Professional Activities