Real-Time and Embedded Systems Lab (original) (raw)

	Sebastian HahnReal-Time and Embedded Systems Lab Universität des SaarlandeseMail: The above mail address should continue to work and I am happy to receive interesting mails.

Short CV

I joined the group of Jan Reineke in 2013. Prior to that, I worked on relational cache analysis in the group of Reinhard Wilhelm advised by Daniel Grund. I completed my B.Sc. on relational cache analysis in late 2011. Since 2012, I am a member of the Graduate School of Computer Science at Saarland University. I received my M.Sc. on a formal definition of timing compositionality in early 2015.

Until the end of 2015, I was part of the DFG SFB/TR 14 Automatic Verification and Analysis of Complex Systems working on timing compositionality.
From 2017 on, I work on timing-predictable processor designs and corresponding timing analyses within the DFG project "PEP: Precise and Efficient Prediction of Good Worst-case Performance for Contemporary and Future Architectures".

In April 2019, I defended my doctoral thesis about how to enable compositional analysis by analysis and hardware design as well as the design and implementation of the timing predictable strictly in-order pipeline. From May to September 2019, I worked as a postdoc continuing my research on predictable hardware design as well as exact cache persistence analysis.
From October 2019 on, I work at AbsInt Angewandte Informatik GmbH in the broader field of static program analysis.

Research Interests

If you want to discuss something related to my research interests, please do not hesitate to contact me.

• Computer Architecture, especially reconciling performance with timing predictability and security
• FPGA programming
• Embedded Systems
• Static Program Analysis, especially Timing Analysis
• Timing compositionality

Teaching

Winter 2016/2017, Winter 2018/2019

• Seminar: Hardware Design

Summer 2015, Winter 2017/2018

• Advanced Course: Verification of Real-Time Systems

Summer 2014, Summer 2016, Summer 2017

• Basic Course: Systemarchitektur

Winter 2012/2013

• Advanced Course: Development of Safety-Critical Embedded Systems

Summer 2012

• Core Course: Embedded Systems

Thesis Advisor

• Claus Faymonville
  Evaluating compositional timing analyses
  Master Thesis, Saarland University, 2015
• Benjamin Meyer
  Development of a Controller for the Automated Reconnection of Trolleybus Poles
  Master Thesis, Saarland University, 2015
• Tobias Blaß
  Array-aware Cache Analysis for Write-through and Write-back Caches
  Master Thesis, Saarland University, 2016

Publications

•Journal Papers •Conference and Workshop Papers •PhD Thesis •Masters Thesis •Bachelors Thesis •Other •

Journal Papers

1. Design and analysis of SIC: a provably timing-predictable pipelined processor core
   S. Hahn and J. Reineke
   Real-Time Systems, November 2019
   [doi] [bib]
   @article{Hahn2019b,
   title = {Design and analysis of {SIC}: a provably timing-predictable pipelined processor core},
   author = {Hahn, Sebastian and Reineke, Jan},
   day = {15},
   doi = {10.1007/s11241-019-09341-z},
   issn = {1573-1383},
   journal = {Real-Time Systems},
   month = {Nov},
   url = {https://doi.org/10.1007/s11241-019-09341-z},
   year = {2019}
   }
2. Towards compositionality in execution time analysis: definition and challenges
   S. Hahn, J. Reineke, and R. Wilhelm
   SIGBED Review, 12(1), 2015
   [doi] [bib]
   @article{Hahn15,
   title = {Towards compositionality in execution time analysis: definition and challenges},
   author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
   bibsource = {dblp computer science bibliography, http://dblp.org},
   biburl = {http://dblp.uni-trier.de/rec/bib/journals/sigbed/0001RW15},
   doi = {10.1145/2752801.2752805},
   journal = {{SIGBED} Review},
   number = {1},
   pages = {28--36},
   timestamp = {Sat, 25 Apr 2015 19:50:05 +0200},
   url = {http://doi.acm.org/10.1145/2752801.2752805},
   volume = {12},
   year = {2015}
   }

Conference and Workshop Papers

1. LLVMTA: An LLVM-Based WCET Analysis Tool
   S. Hahn, M. Jacobs, N. Hölscher, K. Chen, J. Chen, and J. Reineke
   WCET, 2022
   [doi] [bib]
   @inproceedings{hahn_et_al:OASIcs.WCET.2022.2,
   title = {{LLVMTA: An LLVM-Based WCET Analysis Tool}},
   address = {Dagstuhl, Germany},
   annote = {Keywords: WCET analysis, low-level analysis, LLVM},
   author = {Hahn, Sebastian and Jacobs, Michael and H{"o}lscher, Nils and Chen, Kuan-Hsun and Chen, Jian-Jia and Reineke, Jan},
   booktitle = {20th International Workshop on Worst-Case Execution Time Analysis (WCET 2022)},
   doi = {10.4230/OASIcs.WCET.2022.2},
   editor = {Ballabriga, Cl'{e}ment},
   isbn = {978-3-95977-244-0},
   issn = {2190-6807},
   pages = {2:1--2:17},
   publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{"u}r Informatik},
   series = {Open Access Series in Informatics (OASIcs)},
   url = {https://drops.dagstuhl.de/opus/volltexte/2022/16624},
   urn = {urn:nbn:de:0030-drops-166242},
   volume = {103},
   year = {2022}
   }
2. Cache Persistence Analysis: Finally Exact
   G. Stock, S. Hahn, and J. Reineke
   RTSS, December 2019
   [bib]
   @inproceedings{Stock19,
   title = {Cache Persistence Analysis: Finally Exact},
   author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
   booktitle = {RTSS},
   month = {Dec},
   year = {2019}
   }
3. Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
   S. Hahn and J. Reineke
   RTSS, December 2018
   [pdf] [pdf slides] [bib]
   @inproceedings{Hahn18,
   title = {Design and Analysis of {SIC}: A Provably Timing-Predictable Pipelined Processor Core},
   author = {Hahn, Sebastian and Reineke, Jan},
   booktitle = {RTSS},
   month = {Dec},
   year = {2018}
   }
4. Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis
   D. Shah, S. Hahn, and J. Reineke
   WCET, July 2018
   [bib]
   @inproceedings{Shah18,
   title = {Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis},
   author = {Shah, Darshit and Hahn, Sebastian and Reineke, Jan},
   booktitle = {15th International Workshop on Worst-Case Execution Time Analysis, {WCET} 2018, July 3, 2018, Barcelona, Spain},
   month = {Jul},
   year = {2018}
   }
5. Write-Back Caches in WCET Analysis
   T. Blaß , S. Hahn, and J. Reineke
   ECRTS, 2017
   [doi] [pdf] [pdf slides] [bib]
   @inproceedings{Blass17,
   title = {Write-Back Caches in {WCET} Analysis},
   author = {Bla{\ss }, Tobias and Hahn, Sebastian and Reineke, Jan},
   booktitle = {29th Euromicro Conference on Real-Time Systems, {ECRTS} 2017, June 27-30, 2017, Dubrovnik, Croatia},
   doi = {10.4230/LIPIcs.ECRTS.2017.26},
   pages = {26:1--26:22},
   url = {https://doi.org/10.4230/LIPIcs.ECRTS.2017.26},
   year = {2017}
   }
6. Enabling Compositionality for Multicore Timing Analysis
   S. Hahn, M. Jacobs, and J. Reineke
   RTNS, October 2016
   [doi] [pdf] [bib]
   @inproceedings{Hahn16,
   title = {Enabling Compositionality for Multicore Timing Analysis},
   author = {Hahn, Sebastian and Jacobs, Michael and Reineke, Jan},
   booktitle = {Proceedings of the 24th International Conference on Real-Time Networks and Systems},
   doi = {10.1145/2997465.2997471},
   month = {Oct},
   url = {http://embedded.cs.uni-saarland.de/publications/EnablingCompositionalityRTNS2016.pdf},
   year = {2016}
   }
7. A Framework for the Derivation of WCET Analyses for Multi-core Processors
   Michael Jacobs, Sebastian Hahn, and Sebastian Hack
   ECRTS, 2016
   [bib]
   @inproceedings{Jacobs2016,
   author = {Michael Jacobs and
   Sebastian Hahn and
   Sebastian Hack},

title = {A Framework for the Derivation of {WCET} Analyses for Multi-core Processors},
booktitle = {Proceedings of the 28th Euromicro Conference on Real-Time Systems, {ECRTS} 2016, Toulouse,
France},
pages = {141--151},
year = {2016},
url = {https://doi.org/10.1109/ECRTS.2016.19},
} 8. Toward Compact Abstractions for Processor Pipelines
S. Hahn, J. Reineke, and R. Wilhelm
Correct System Design - Symposium in Honor of Ernst-Rüdiger Olderog on the Occasion of His 60th Birthday, Oldenburg, Germany, September 8-9, 2015. Proceedings, 2015
[doi] [pdf] [bib]
@inproceedings{Hahn15b,
title = {Toward Compact Abstractions for Processor Pipelines},
author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
booktitle = {Correct System Design - Symposium in Honor of Ernst-R{{"u}}diger Olderog on the Occasion of His 60th Birthday, Oldenburg, Germany, September 8-9, 2015. Proceedings},
doi = {10.1007/978-3-319-23506-6_14},
editor = {Meyer, Roland and Platzer, André and Wehrheim, Heike},
pages = {205--220},
url = {http://dx.doi.org/10.1007/978-3-319-23506-6_14},
year = {2015}
} 9. WCET Analysis for Multi-Core Processors with Shared Buses and Event-Driven Bus Arbitration
Michael Jacobs, Sebastian Hahn, and Sebastian Hack
RTNS, 2015
[bib]
@inproceedings{Jacobs2015,
author = {Michael Jacobs and
Sebastian Hahn and
Sebastian Hack},
title = {{WCET} Analysis for Multi-Core Processors with Shared Buses and Event-Driven Bus Arbitration},
booktitle = {Proceedings of the 23nd International Conference on Real-Time Networks and Systems, {RTNS} 2015, Lille, France},
year = {2015}
} 10. Selfish-LRU: Preemption-aware caching for predictability and performance
J. Reineke, S. Altmeyer, D. Grund, S. Hahn, and C. Maiza
RTAS, April 2014
[doi] [pdf] [pdf slides] [bib]
@inproceedings{Reineke14b,
title = {Selfish-LRU: Preemption-aware caching for predictability and performance},
author = {Reineke, Jan and Altmeyer, Sebastian and Grund, Daniel and Hahn, Sebastian and Maiza, Claire},
booktitle = {20th {IEEE} Real-Time and Embedded Technology and Applications Symposium, {RTAS} 2014, Berlin, Germany, April 15-17, 2014},
doi = {10.1109/RTAS.2014.6925997},
month = {Apr},
pages = {135--144},
url = {http://embedded.cs.uni-saarland.de/publications/SelfishLRU-RTAS-2014.pdf},
year = {2014}
} 11. Impact of Resource Sharing on Performance and Performance Prediction: A Survey
A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. Moin, J. Reineke, B. Schommer, and R. Wilhelm
CONCUR, August 2013
[doi] [pdf] [bib]
@inproceedings{Abel13b,
title = {Impact of Resource Sharing on Performance and Performance Prediction: {A} Survey},
author = {Abel, Andreas and Benz, Florian and Doerfert, Johannes and D"orr, Barbara and Hahn, Sebastian and Haupenthal, Florian and Jacobs, Michael and Moin, Amir H. and Reineke, Jan and Schommer, Bernhard and Wilhelm, Reinhard},
booktitle = {{CONCUR} 2013 - Concurrency Theory - 24th International Conference, {CONCUR} 2013, Buenos Aires, Argentina, August 27-30, 2013. Proceedings},
doi = {10.1007/978-3-642-40184-8_3},
month = {Aug},
pages = {25--43},
url = {http://embedded.cs.uni-saarland.de/publications/ResourceSharingSurvey.pdf},
year = {2013}
} 12. Towards Compositionality in Execution Time Analysis -- Definition and Challenges
S. Hahn, J. Reineke, and R. Wilhelm
CRTS, December 2013
[pdf] [bib]
@inproceedings{Hahn13,
title = {Towards Compositionality in Execution Time Analysis -- Definition and Challenges},
author = {Hahn, Sebastian and Reineke, Jan and Wilhelm, Reinhard},
booktitle = {6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS)},
month = {Dec},
url = {http://embedded.cs.uni-saarland.de/publications/TowardsCompositionality.pdf},
year = {2013}
}

PhD Thesis

1. On Static Execution-Time Analysis---Compositionality, Pipeline Abstraction, and Predictable Hardware
   Sebastian Hahn
   Universität des Saarlandes, 2019
   [pdf] [bib]
   @phdthesis{Hahn2019,
   author = {Sebastian Hahn},
   title = {On Static Execution-Time Analysis---Compositionality, Pipeline Abstraction, and Predictable Hardware},
   school = {Universit"at des Saarlandes},
   year = {2019},
   url = {https://d-nb.info/1187241180/34}
   }

Masters Thesis

1. Defining Compositionalty in Execution Time Analysis
   S. Hahn
   Universität des Saarlandes, Germany, 2014
   [pdf] [bib]
   @mastersthesis{Hahn14,
   title = {Defining Compositionalty in Execution Time Analysis},
   author = {Hahn, Sebastian},
   school = {Universit"at des Saarlandes, Germany},
   type = {master's thesis},
   year = {2014}
   }

Bachelors Thesis

1. Towards Relational Cache Analysis
   S. Hahn
   Saarland University, 2011
   [bib]
   @mastersthesis{Hahn11,
   title = {Towards Relational Cache Analysis},
   author = {Hahn, Sebastian},
   url = {http://embedded.cs.uni-sb.de/publications/RelCanaBSC2011.pdf},
   school = {Saarland University},
   type = {bachelor's thesis},
   year = {2011}
   }

Other

1. Cache Persistence Analysis: Finally Exact
   G. Stock, S. Hahn, and J. Reineke
   arXiv, abs/1909.04374, 2019
   [bib]
   @article{Stock19b,
   title = {Cache Persistence Analysis: Finally Exact},
   archiveprefix = {arXiv},
   author = {Stock, Gregory and Hahn, Sebastian and Reineke, Jan},
   eprint = {1909.04374},
   journal = {CoRR},
   url = {http://arxiv.org/abs/1909.04374},
   volume = {abs/1909.04374},
   year = {2019}
   }

A list of publications can also be found on DBLP.