Reset asserted level - Asserted or active level of the reset input signal - MATLAB (original) (raw)

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Asserted or active level of the reset input signal

Model Configuration Pane: HDL Code Generation / Global Settings

Description

The Reset asserted level parameter specifies whether the asserted or active level of the reset input signal is active-high or active-low.

Settings

Active-high (default) | Active-low

Active-high

Specifies that the asserted level of the reset input signal is active-high. For example, this code fragment checks whether reset is active-high before populating the delay_pipeline register:

Delay_Pipeline_Process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0')); . . .

To reset the registers in your design when you input a logic high value to the value of the Reset input port parameter, setReset asserted level toActive-high.

Active-low

Specifies that the asserted level of the reset input signal is active-low. For example, this code fragment checks whether reset is active-low before populating the delay_pipeline register:

Delay_Pipeline_Process : PROCESS (clk, reset) BEGIN IF reset = '0' THEN delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0')); . . .

To reset the registers in your design when you input a logic low value to the value of the Reset input port parameter, setReset asserted level toActive-low.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to set this property for a subsystem named symmetric_fir in a model named sfir_fixed, use one of these methods:

Programmatic Use

Parameter: ResetAssertedLevel
Type: character vector
Value: "active-high" | "active-low"
Default: "active-high"

Version History

Introduced in R2012a