Model Referencing for HDL Code Generation - MATLAB & Simulink (original) (raw)

Main Content

Model referencing in your DUT subsystem enables you to:

• Partition a large design into a hierarchy of smaller designs for reuse, modular development, and accelerated simulation. See Model References: Build Model Design Using Smaller Partitions.
• Create protected models to obscure model contents, which is useful for distribution. See Create Protected Models to Conceal Contents and Generate HDL Code.
• Only generate code when reference model changes. The code generator complies a model reference only when it detects a change in the model reference. For more information on incremental code generation, see Generate Incremental HDL Code for Referenced Models.

For more information on model references, see Model Reference Behavior and Capabilities.

Generating HDL Code for Referenced Models

You can generate HDL code for the referenced model using the GUI or the command line.

Using GUI

1. Right-click the Model block and select HDL Code >HDL Block Properties.
2. In HDL Block Properties dialog box, set the Architecture property to ModelReference.
3. Generate HDL code from your DUT subsystem.

Using Command Line

1. Set the Architecture property of the Model block toModelReference. For example, suppose that you have a DUT subsystem named mydut, that includes a model reference,referenced_model. Enter this command:
   hdlset_param('mydut/referenced_model', ...
   'Architecture', 'ModelReference');
2. Generate HDL code for your DUT subsystem.

Generate Code for Model Arguments

To generate a single Verilog® or SystemVerilog module or VHDL® entity for instances of a referenced model with different model argument values, see Generate Parameterized Code for Referenced Models.

Limitations

• Model blocks must use the default values for the block parameters.
• If there are multiple model references to the same model, they must maintain identical HDL block properties.
• HDL Coder™ cannot move registers across a model reference. Therefore, you cannot use these optimizations with models that contain model references:
  • Distributed pipelining
  • Constrained output pipelining
  • Streaming
  • Clock-rate pipelining
• To optimize a referenced model for resource sharing, the model reference must have the same final rate after any optimizations and rate propagation. You cannot apply this optimization if the model references have differing final rates.
• When generating HDL code from model references, the generated model, validation model, and cosimulation model may encounter compile or simulate errors. To fix these issues, ensure that you load the models and they are on the search path.

See Also

Model Settings

• Generate VHDL or SystemVerilog code for model references into a single library | Rebuild | Scalarize ports

Topics

• Model References: Build Model Design Using Smaller Partitions
• Prepare the Parent Model
• Generate Parameterized Code for Referenced Models
• Create Protected Models to Conceal Contents and Generate HDL Code