Generate Parameterized Code for Referenced Models - MATLAB & Simulink (original) (raw)

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To generate parameterized code for referenced models, use model arguments. You can use model arguments in a masked or unmasked Model block.

HDL Coder™ generates a single VHDL® entity, Verilog® or SystemVerilog module for the referenced model, even if the DUT has multiple instances of the referenced model. In the generated code, each model argument is a VHDLgeneric or a Verilog or SystemVerilog parameter.

Parameterize Referenced Model for HDL Code Generation

1. In the referenced model, create one or more model arguments.
   To learn how to create a model argument, see Specify a Different Value for Each Instance of a Reusable Model.
2. In the referenced model, use each model argument parameter in aGain or Constant block.
3. In the DUT, for each model reference, in the Model arguments table, enter values for each model argument.
   Alternatively, create a model mask for the referenced model. In the DUT, for each model reference, enter values for each model argument.
4. Generate code for the DUT.

Restrictions

Model argument values:

• Must be scalar.
• Cannot be complex.
• Cannot be enumerated data.

See Also

Topics

• Generate Reusable Code for Subsystems
• Generate DUT Ports for Tunable Parameters
• Specify a Different Value for Each Instance of a Reusable Model
• Model Referencing for HDL Code Generation